drm: rcar-du: lvds: D3/E3 support
The LVDS encoders in the D3 and E3 SoCs differ significantly from those in the other R-Car Gen3 family members: - The LVDS PLL architecture is more complex and requires computing PLL parameters manually. - The PLL uses external clocks as inputs, which need to be retrieved from DT. - In addition to the different PLL setup, the startup sequence has changed *again* (seems someone had trouble making his/her mind). Supporting all this requires DT bindings extensions for external clocks, brand new PLL setup code, and a few quirks to handle the differences in the startup sequence. The implementation doesn't support all hardware features yet, namely - Using the LV[01] clocks generated by the CPG as PLL input. - Providing the LVDS PLL clock to the DU for use with the RGB output. Those features can be added later when the need will arise. Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Tested-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Reviewed-by: Ulrich Hecht <uli+renesas@fpond.eu> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>hifive-unleashed-5.1
Laurent Pinchart
parent
399d9f2f19
commit
c25c013611
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@ -24,6 +24,8 @@
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#include "rcar_lvds_regs.h"
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struct rcar_lvds;
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/* Keep in sync with the LVDCR0.LVMD hardware register values. */
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enum rcar_lvds_mode {
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RCAR_LVDS_MODE_JEIDA = 0,
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@ -31,14 +33,16 @@ enum rcar_lvds_mode {
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RCAR_LVDS_MODE_VESA = 4,
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};
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#define RCAR_LVDS_QUIRK_LANES (1 << 0) /* LVDS lanes 1 and 3 inverted */
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#define RCAR_LVDS_QUIRK_GEN2_PLLCR (1 << 1) /* LVDPLLCR has gen2 layout */
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#define RCAR_LVDS_QUIRK_GEN3_LVEN (1 << 2) /* LVEN bit needs to be set */
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/* on R8A77970/R8A7799x */
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#define RCAR_LVDS_QUIRK_LANES BIT(0) /* LVDS lanes 1 and 3 inverted */
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#define RCAR_LVDS_QUIRK_GEN3_LVEN BIT(1) /* LVEN bit needs to be set on R8A77970/R8A7799x */
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#define RCAR_LVDS_QUIRK_PWD BIT(2) /* PWD bit available (all of Gen3 but E3) */
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#define RCAR_LVDS_QUIRK_EXT_PLL BIT(3) /* Has extended PLL */
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#define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */
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struct rcar_lvds_device_info {
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unsigned int gen;
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unsigned int quirks;
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void (*pll_setup)(struct rcar_lvds *lvds, unsigned int freq);
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};
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struct rcar_lvds {
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@ -52,7 +56,11 @@ struct rcar_lvds {
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struct drm_panel *panel;
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void __iomem *mmio;
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struct clk *clock;
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struct {
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struct clk *mod; /* CPG module clock */
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struct clk *extal; /* External clock */
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struct clk *dotclkin[2]; /* External DU clocks */
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} clocks;
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bool enabled;
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struct drm_display_mode display_mode;
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@ -128,33 +136,216 @@ static const struct drm_connector_funcs rcar_lvds_conn_funcs = {
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};
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/* -----------------------------------------------------------------------------
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* Bridge
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* PLL Setup
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*/
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static u32 rcar_lvds_lvdpllcr_gen2(unsigned int freq)
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static void rcar_lvds_pll_setup_gen2(struct rcar_lvds *lvds, unsigned int freq)
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{
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if (freq < 39000)
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return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
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else if (freq < 61000)
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return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
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else if (freq < 121000)
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return LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
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u32 val;
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if (freq < 39000000)
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val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
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else if (freq < 61000000)
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val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
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else if (freq < 121000000)
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val = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
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else
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return LVDPLLCR_PLLDLYCNT_150M;
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val = LVDPLLCR_PLLDLYCNT_150M;
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rcar_lvds_write(lvds, LVDPLLCR, val);
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}
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static u32 rcar_lvds_lvdpllcr_gen3(unsigned int freq)
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static void rcar_lvds_pll_setup_gen3(struct rcar_lvds *lvds, unsigned int freq)
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{
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if (freq < 42000)
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return LVDPLLCR_PLLDIVCNT_42M;
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else if (freq < 85000)
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return LVDPLLCR_PLLDIVCNT_85M;
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else if (freq < 128000)
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return LVDPLLCR_PLLDIVCNT_128M;
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u32 val;
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if (freq < 42000000)
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val = LVDPLLCR_PLLDIVCNT_42M;
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else if (freq < 85000000)
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val = LVDPLLCR_PLLDIVCNT_85M;
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else if (freq < 128000000)
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val = LVDPLLCR_PLLDIVCNT_128M;
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else
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return LVDPLLCR_PLLDIVCNT_148M;
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val = LVDPLLCR_PLLDIVCNT_148M;
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rcar_lvds_write(lvds, LVDPLLCR, val);
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}
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struct pll_info {
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unsigned long diff;
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unsigned int pll_m;
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unsigned int pll_n;
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unsigned int pll_e;
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unsigned int div;
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u32 clksel;
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};
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static void rcar_lvds_d3_e3_pll_calc(struct rcar_lvds *lvds, struct clk *clk,
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unsigned long target, struct pll_info *pll,
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u32 clksel)
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{
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unsigned long output;
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unsigned long fin;
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unsigned int m_min;
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unsigned int m_max;
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unsigned int m;
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int error;
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if (!clk)
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return;
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/*
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* The LVDS PLL is made of a pre-divider and a multiplier (strangely
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* enough called M and N respectively), followed by a post-divider E.
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*
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* ,-----. ,-----. ,-----. ,-----.
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* Fin --> | 1/M | -Fpdf-> | PFD | --> | VCO | -Fvco-> | 1/E | --> Fout
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* `-----' ,-> | | `-----' | `-----'
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* | `-----' |
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* | ,-----. |
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* `-------- | 1/N | <-------'
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* `-----'
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*
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* The clock output by the PLL is then further divided by a programmable
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* divider DIV to achieve the desired target frequency. Finally, an
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* optional fixed /7 divider is used to convert the bit clock to a pixel
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* clock (as LVDS transmits 7 bits per lane per clock sample).
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*
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* ,-------. ,-----. |\
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* Fout --> | 1/DIV | --> | 1/7 | --> | |
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* `-------' | `-----' | | --> dot clock
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* `------------> | |
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* |/
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*
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* The /7 divider is optional when the LVDS PLL is used to generate a
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* dot clock for the DU RGB output, without using the LVDS encoder. We
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* don't support this configuration yet.
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*
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* The PLL allowed input frequency range is 12 MHz to 192 MHz.
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*/
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fin = clk_get_rate(clk);
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if (fin < 12000000 || fin > 192000000)
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return;
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/*
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* The comparison frequency range is 12 MHz to 24 MHz, which limits the
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* allowed values for the pre-divider M (normal range 1-8).
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*
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* Fpfd = Fin / M
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*/
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m_min = max_t(unsigned int, 1, DIV_ROUND_UP(fin, 24000000));
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m_max = min_t(unsigned int, 8, fin / 12000000);
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for (m = m_min; m <= m_max; ++m) {
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unsigned long fpfd;
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unsigned int n_min;
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unsigned int n_max;
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unsigned int n;
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/*
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* The VCO operating range is 900 Mhz to 1800 MHz, which limits
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* the allowed values for the multiplier N (normal range
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* 60-120).
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*
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* Fvco = Fin * N / M
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*/
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fpfd = fin / m;
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n_min = max_t(unsigned int, 60, DIV_ROUND_UP(900000000, fpfd));
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n_max = min_t(unsigned int, 120, 1800000000 / fpfd);
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for (n = n_min; n < n_max; ++n) {
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unsigned long fvco;
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unsigned int e_min;
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unsigned int e;
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/*
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* The output frequency is limited to 1039.5 MHz,
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* limiting again the allowed values for the
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* post-divider E (normal value 1, 2 or 4).
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*
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* Fout = Fvco / E
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*/
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fvco = fpfd * n;
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e_min = fvco > 1039500000 ? 1 : 0;
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for (e = e_min; e < 3; ++e) {
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unsigned long fout;
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unsigned long diff;
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unsigned int div;
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/*
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* Finally we have a programable divider after
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* the PLL, followed by a an optional fixed /7
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* divider.
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*/
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fout = fvco / (1 << e) / 7;
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div = DIV_ROUND_CLOSEST(fout, target);
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diff = abs(fout / div - target);
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if (diff < pll->diff) {
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pll->diff = diff;
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pll->pll_m = m;
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pll->pll_n = n;
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pll->pll_e = e;
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pll->div = div;
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pll->clksel = clksel;
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if (diff == 0)
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goto done;
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}
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}
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}
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}
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done:
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output = fin * pll->pll_n / pll->pll_m / (1 << pll->pll_e)
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/ 7 / pll->div;
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error = (long)(output - target) * 10000 / (long)target;
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dev_dbg(lvds->dev,
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"%pC %lu Hz -> Fout %lu Hz (target %lu Hz, error %d.%02u%%), PLL M/N/E/DIV %u/%u/%u/%u\n",
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clk, fin, output, target, error / 100,
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error < 0 ? -error % 100 : error % 100,
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pll->pll_m, pll->pll_n, pll->pll_e, pll->div);
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}
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static void rcar_lvds_pll_setup_d3_e3(struct rcar_lvds *lvds, unsigned int freq)
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{
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struct pll_info pll = { .diff = (unsigned long)-1 };
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u32 lvdpllcr;
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rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[0], freq, &pll,
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LVDPLLCR_CKSEL_DU_DOTCLKIN(0));
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rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.dotclkin[1], freq, &pll,
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LVDPLLCR_CKSEL_DU_DOTCLKIN(1));
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rcar_lvds_d3_e3_pll_calc(lvds, lvds->clocks.extal, freq, &pll,
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LVDPLLCR_CKSEL_EXTAL);
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lvdpllcr = LVDPLLCR_PLLON | pll.clksel | LVDPLLCR_CLKOUT
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| LVDPLLCR_PLLN(pll.pll_n - 1) | LVDPLLCR_PLLM(pll.pll_m - 1);
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if (pll.pll_e > 0)
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lvdpllcr |= LVDPLLCR_STP_CLKOUTE | LVDPLLCR_OUTCLKSEL
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| LVDPLLCR_PLLE(pll.pll_e - 1);
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rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
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if (pll.div > 1)
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/*
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* The DIVRESET bit is a misnomer, setting it to 1 deasserts the
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* divisor reset.
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*/
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rcar_lvds_write(lvds, LVDDIV, LVDDIV_DIVSEL |
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LVDDIV_DIVRESET | LVDDIV_DIV(pll.div - 1));
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else
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rcar_lvds_write(lvds, LVDDIV, 0);
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}
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/* -----------------------------------------------------------------------------
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* Bridge
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*/
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static void rcar_lvds_enable(struct drm_bridge *bridge)
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{
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struct rcar_lvds *lvds = bridge_to_rcar_lvds(bridge);
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@ -164,14 +355,13 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
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* do we get a state pointer?
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*/
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struct drm_crtc *crtc = lvds->bridge.encoder->crtc;
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u32 lvdpllcr;
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u32 lvdhcr;
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u32 lvdcr0;
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int ret;
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WARN_ON(lvds->enabled);
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ret = clk_prepare_enable(lvds->clock);
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ret = clk_prepare_enable(lvds->clocks.mod);
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if (ret < 0)
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return;
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@ -196,12 +386,13 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
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rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
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if (lvds->info->quirks & RCAR_LVDS_QUIRK_DUAL_LINK) {
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/* Disable dual-link mode. */
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rcar_lvds_write(lvds, LVDSTRIPE, 0);
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}
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/* PLL clock configuration. */
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if (lvds->info->quirks & RCAR_LVDS_QUIRK_GEN2_PLLCR)
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lvdpllcr = rcar_lvds_lvdpllcr_gen2(mode->clock);
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else
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lvdpllcr = rcar_lvds_lvdpllcr_gen3(mode->clock);
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rcar_lvds_write(lvds, LVDPLLCR, lvdpllcr);
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lvds->info->pll_setup(lvds, mode->clock * 1000);
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/* Set the LVDS mode and select the input. */
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lvdcr0 = lvds->mode << LVDCR0_LVMD_SHIFT;
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@ -220,11 +411,16 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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}
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/* Turn the PLL on. */
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lvdcr0 |= LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
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/*
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* Turn the PLL on (simple PLL only, extended PLL is fully
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* controlled through LVDPLLCR).
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*/
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lvdcr0 |= LVDCR0_PLLON;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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}
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if (lvds->info->gen > 2) {
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if (lvds->info->quirks & RCAR_LVDS_QUIRK_PWD) {
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/* Set LVDS normal mode. */
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lvdcr0 |= LVDCR0_PWD;
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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@ -236,8 +432,10 @@ static void rcar_lvds_enable(struct drm_bridge *bridge)
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rcar_lvds_write(lvds, LVDCR0, lvdcr0);
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}
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/* Wait for the startup delay. */
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usleep_range(100, 150);
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if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL)) {
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/* Wait for the PLL startup delay (simple PLL only). */
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usleep_range(100, 150);
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}
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/* Turn the output on. */
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lvdcr0 |= LVDCR0_LVRES;
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@ -264,8 +462,9 @@ static void rcar_lvds_disable(struct drm_bridge *bridge)
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rcar_lvds_write(lvds, LVDCR0, 0);
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rcar_lvds_write(lvds, LVDCR1, 0);
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rcar_lvds_write(lvds, LVDPLLCR, 0);
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clk_disable_unprepare(lvds->clock);
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clk_disable_unprepare(lvds->clocks.mod);
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lvds->enabled = false;
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}
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@ -446,6 +645,60 @@ done:
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return ret;
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}
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static struct clk *rcar_lvds_get_clock(struct rcar_lvds *lvds, const char *name,
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bool optional)
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{
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struct clk *clk;
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clk = devm_clk_get(lvds->dev, name);
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if (!IS_ERR(clk))
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return clk;
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if (PTR_ERR(clk) == -ENOENT && optional)
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return NULL;
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if (PTR_ERR(clk) != -EPROBE_DEFER)
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dev_err(lvds->dev, "failed to get %s clock\n",
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name ? name : "module");
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return clk;
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}
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static int rcar_lvds_get_clocks(struct rcar_lvds *lvds)
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{
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lvds->clocks.mod = rcar_lvds_get_clock(lvds, NULL, false);
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if (IS_ERR(lvds->clocks.mod))
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return PTR_ERR(lvds->clocks.mod);
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/*
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* LVDS encoders without an extended PLL have no external clock inputs.
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*/
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if (!(lvds->info->quirks & RCAR_LVDS_QUIRK_EXT_PLL))
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return 0;
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lvds->clocks.extal = rcar_lvds_get_clock(lvds, "extal", true);
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if (IS_ERR(lvds->clocks.extal))
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return PTR_ERR(lvds->clocks.extal);
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lvds->clocks.dotclkin[0] = rcar_lvds_get_clock(lvds, "dclkin.0", true);
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if (IS_ERR(lvds->clocks.dotclkin[0]))
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return PTR_ERR(lvds->clocks.dotclkin[0]);
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lvds->clocks.dotclkin[1] = rcar_lvds_get_clock(lvds, "dclkin.1", true);
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if (IS_ERR(lvds->clocks.dotclkin[1]))
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return PTR_ERR(lvds->clocks.dotclkin[1]);
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/* At least one input to the PLL must be available. */
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if (!lvds->clocks.extal && !lvds->clocks.dotclkin[0] &&
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!lvds->clocks.dotclkin[1]) {
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dev_err(lvds->dev,
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"no input clock (extal, dclkin.0 or dclkin.1)\n");
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return -EINVAL;
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}
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return 0;
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}
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static int rcar_lvds_probe(struct platform_device *pdev)
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{
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||||
struct rcar_lvds *lvds;
|
||||
|
|
@ -475,11 +728,9 @@ static int rcar_lvds_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(lvds->mmio))
|
||||
return PTR_ERR(lvds->mmio);
|
||||
|
||||
lvds->clock = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(lvds->clock)) {
|
||||
dev_err(&pdev->dev, "failed to get clock\n");
|
||||
return PTR_ERR(lvds->clock);
|
||||
}
|
||||
ret = rcar_lvds_get_clocks(lvds);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
drm_bridge_add(&lvds->bridge);
|
||||
|
||||
|
|
@ -497,21 +748,39 @@ static int rcar_lvds_remove(struct platform_device *pdev)
|
|||
|
||||
static const struct rcar_lvds_device_info rcar_lvds_gen2_info = {
|
||||
.gen = 2,
|
||||
.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR,
|
||||
.pll_setup = rcar_lvds_pll_setup_gen2,
|
||||
};
|
||||
|
||||
static const struct rcar_lvds_device_info rcar_lvds_r8a7790_info = {
|
||||
.gen = 2,
|
||||
.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_LANES,
|
||||
.quirks = RCAR_LVDS_QUIRK_LANES,
|
||||
.pll_setup = rcar_lvds_pll_setup_gen2,
|
||||
};
|
||||
|
||||
static const struct rcar_lvds_device_info rcar_lvds_gen3_info = {
|
||||
.gen = 3,
|
||||
.quirks = RCAR_LVDS_QUIRK_PWD,
|
||||
.pll_setup = rcar_lvds_pll_setup_gen3,
|
||||
};
|
||||
|
||||
static const struct rcar_lvds_device_info rcar_lvds_r8a77970_info = {
|
||||
.gen = 3,
|
||||
.quirks = RCAR_LVDS_QUIRK_GEN2_PLLCR | RCAR_LVDS_QUIRK_GEN3_LVEN,
|
||||
.quirks = RCAR_LVDS_QUIRK_PWD | RCAR_LVDS_QUIRK_GEN3_LVEN,
|
||||
.pll_setup = rcar_lvds_pll_setup_gen2,
|
||||
};
|
||||
|
||||
static const struct rcar_lvds_device_info rcar_lvds_r8a77990_info = {
|
||||
.gen = 3,
|
||||
.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_EXT_PLL
|
||||
| RCAR_LVDS_QUIRK_DUAL_LINK,
|
||||
.pll_setup = rcar_lvds_pll_setup_d3_e3,
|
||||
};
|
||||
|
||||
static const struct rcar_lvds_device_info rcar_lvds_r8a77995_info = {
|
||||
.gen = 3,
|
||||
.quirks = RCAR_LVDS_QUIRK_GEN3_LVEN | RCAR_LVDS_QUIRK_PWD
|
||||
| RCAR_LVDS_QUIRK_EXT_PLL | RCAR_LVDS_QUIRK_DUAL_LINK,
|
||||
.pll_setup = rcar_lvds_pll_setup_d3_e3,
|
||||
};
|
||||
|
||||
static const struct of_device_id rcar_lvds_of_table[] = {
|
||||
|
|
@ -523,6 +792,8 @@ static const struct of_device_id rcar_lvds_of_table[] = {
|
|||
{ .compatible = "renesas,r8a7796-lvds", .data = &rcar_lvds_gen3_info },
|
||||
{ .compatible = "renesas,r8a77970-lvds", .data = &rcar_lvds_r8a77970_info },
|
||||
{ .compatible = "renesas,r8a77980-lvds", .data = &rcar_lvds_gen3_info },
|
||||
{ .compatible = "renesas,r8a77990-lvds", .data = &rcar_lvds_r8a77990_info },
|
||||
{ .compatible = "renesas,r8a77995-lvds", .data = &rcar_lvds_r8a77995_info },
|
||||
{ }
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@
|
|||
#define LVDCR0_PLLON (1 << 4)
|
||||
#define LVDCR0_PWD (1 << 2) /* Gen3 only */
|
||||
#define LVDCR0_BEN (1 << 2) /* Gen2 only */
|
||||
#define LVDCR0_LVEN (1 << 1) /* Gen2 only */
|
||||
#define LVDCR0_LVEN (1 << 1)
|
||||
#define LVDCR0_LVRES (1 << 0)
|
||||
|
||||
#define LVDCR1 0x0004
|
||||
|
|
@ -27,21 +27,36 @@
|
|||
#define LVDCR1_CLKSTBY (3 << 0)
|
||||
|
||||
#define LVDPLLCR 0x0008
|
||||
/* Gen2 & V3M */
|
||||
#define LVDPLLCR_CEEN (1 << 14)
|
||||
#define LVDPLLCR_FBEN (1 << 13)
|
||||
#define LVDPLLCR_COSEL (1 << 12)
|
||||
/* Gen2 */
|
||||
#define LVDPLLCR_PLLDLYCNT_150M (0x1bf << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_121M (0x22c << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_60M (0x77b << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_38M (0x69a << 0)
|
||||
#define LVDPLLCR_PLLDLYCNT_MASK (0x7ff << 0)
|
||||
/* Gen3 */
|
||||
/* Gen3 but V3M,D3 and E3 */
|
||||
#define LVDPLLCR_PLLDIVCNT_42M (0x014cb << 0)
|
||||
#define LVDPLLCR_PLLDIVCNT_85M (0x00a45 << 0)
|
||||
#define LVDPLLCR_PLLDIVCNT_128M (0x006c3 << 0)
|
||||
#define LVDPLLCR_PLLDIVCNT_148M (0x046c1 << 0)
|
||||
#define LVDPLLCR_PLLDIVCNT_MASK (0x7ffff << 0)
|
||||
/* D3 and E3 */
|
||||
#define LVDPLLCR_PLLON (1 << 22)
|
||||
#define LVDPLLCR_PLLSEL_PLL0 (0 << 20)
|
||||
#define LVDPLLCR_PLLSEL_LVX (1 << 20)
|
||||
#define LVDPLLCR_PLLSEL_PLL1 (2 << 20)
|
||||
#define LVDPLLCR_CKSEL_LVX (1 << 17)
|
||||
#define LVDPLLCR_CKSEL_EXTAL (3 << 17)
|
||||
#define LVDPLLCR_CKSEL_DU_DOTCLKIN(n) ((5 + (n) * 2) << 17)
|
||||
#define LVDPLLCR_OCKSEL (1 << 16)
|
||||
#define LVDPLLCR_STP_CLKOUTE (1 << 14)
|
||||
#define LVDPLLCR_OUTCLKSEL (1 << 12)
|
||||
#define LVDPLLCR_CLKOUT (1 << 11)
|
||||
#define LVDPLLCR_PLLE(n) ((n) << 10)
|
||||
#define LVDPLLCR_PLLN(n) ((n) << 3)
|
||||
#define LVDPLLCR_PLLM(n) ((n) << 0)
|
||||
|
||||
#define LVDCTRCR 0x000c
|
||||
#define LVDCTRCR_CTR3SEL_ZERO (0 << 12)
|
||||
|
|
@ -71,4 +86,26 @@
|
|||
#define LVDCHCR_CHSEL_CH(n, c) ((((c) - (n)) & 3) << ((n) * 4))
|
||||
#define LVDCHCR_CHSEL_MASK(n) (3 << ((n) * 4))
|
||||
|
||||
/* All registers below are specific to D3 and E3 */
|
||||
#define LVDSTRIPE 0x0014
|
||||
#define LVDSTRIPE_ST_TRGSEL_DISP (0 << 2)
|
||||
#define LVDSTRIPE_ST_TRGSEL_HSYNC_R (1 << 2)
|
||||
#define LVDSTRIPE_ST_TRGSEL_HSYNC_F (2 << 2)
|
||||
#define LVDSTRIPE_ST_SWAP (1 << 1)
|
||||
#define LVDSTRIPE_ST_ON (1 << 0)
|
||||
|
||||
#define LVDSCR 0x0018
|
||||
#define LVDSCR_DEPTH(n) (((n) - 1) << 29)
|
||||
#define LVDSCR_BANDSET (1 << 28)
|
||||
#define LVDSCR_TWGCNT(n) ((((n) - 256) / 16) << 24)
|
||||
#define LVDSCR_SDIV(n) ((n) << 22)
|
||||
#define LVDSCR_MODE (1 << 21)
|
||||
#define LVDSCR_RSTN (1 << 20)
|
||||
|
||||
#define LVDDIV 0x001c
|
||||
#define LVDDIV_DIVSEL (1 << 8)
|
||||
#define LVDDIV_DIVRESET (1 << 7)
|
||||
#define LVDDIV_DIVSTP (1 << 6)
|
||||
#define LVDDIV_DIV(n) ((n) << 0)
|
||||
|
||||
#endif /* __RCAR_LVDS_REGS_H__ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue