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cxl: Fix timebase synchronization status on P9 

The PSL Timebase register is updated by the PSL to maintain the
timebase.

On P9, the Timebase value is only provided by the CAPP as received the
last time a timebase request was performed.

The timebase requests are initiated through the adapter configuration
or application registers.

The specific sysfs entry "/sys/class/cxl/cardxx/psl_timebase_synced"
is now dynamically updated according the content of the PSL Timebase
register.

Fixes: f24be42aab ("cxl: Add psl9 specific code")
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Vaibhav Jain <vaibhav@linux.vnet.ibm.com>
Acked-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Acked-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
hifive-unleashed-5.1
Christophe Lombard 2018-02-20 14:48:56 +01:00 committed by Michael Ellerman
parent 014a32b30e
commit c2be663d53
2 changed files with 12 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
drivers/misc/cxl/pci.c
View File

@ -659,9 +659,6 @@ static u64 timebase_read_xsl(struct cxl *adapter)
static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
{
u64 psl_tb;
int delta;
unsigned int retry = 0;
struct device_node *np;
adapter->psl_timebase_synced = false;
@ -689,20 +686,6 @@ static void cxl_setup_psl_timebase(struct cxl *adapter, struct pci_dev *dev)
cxl_p1_write(adapter, CXL_PSL_Control, 0x0000000000000000);
cxl_p1_write(adapter, CXL_PSL_Control, CXL_PSL_Control_tb);
/* Wait until CORE TB and PSL TB difference <= 16usecs */
do {
msleep(1);
if (retry++ > 5) {
dev_info(&dev->dev, "PSL timebase can't synchronize\n");
return;
}
psl_tb = adapter->native->sl_ops->timebase_read(adapter);
delta = mftb() - psl_tb;
if (delta < 0)
delta = -delta;
} while (tb_to_ns(delta) > 16000);
adapter->psl_timebase_synced = true;
return;
}

12
drivers/misc/cxl/sysfs.c
View File

@ -62,7 +62,19 @@ static ssize_t psl_timebase_synced_show(struct device *device,
char *buf)
{
struct cxl *adapter = to_cxl_adapter(device);
u64 psl_tb, delta;
/* Recompute the status only in native mode */
if (cpu_has_feature(CPU_FTR_HVMODE)) {
psl_tb = adapter->native->sl_ops->timebase_read(adapter);
delta = abs(mftb() - psl_tb);
/* CORE TB and PSL TB difference <= 16usecs ? */
adapter->psl_timebase_synced = (tb_to_ns(delta) < 16000) ? true : false;
pr_devel("PSL timebase %s - delta: 0x%016llx\n",
(tb_to_ns(delta) < 16000) ? "synchronized" :
"not synchronized", tb_to_ns(delta));
}
return scnprintf(buf, PAGE_SIZE, "%i\n", adapter->psl_timebase_synced);
}