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drm/i915: unify first-stage engine struct setup 

intel_lrc.c has a table of "logical rings" (meaning engines), while
intel_ringbuffer.c has separately open-coded initialisation for each
engine. We can deduplicate this somewhat by using the same first-stage
engine-setup function for both modes.

So here we expose the function that transfers information from the
static table of (all) known engines to the dev_priv->engine array of
engines available on this device (adjusting the names along the way)
and then embed calls to it in both the LRC and the legacy-mode setup.

Signed-off-by: Dave Gordon <david.s.gordon@intel.com>
Reviewed-by: Chris Wilson <chris-wilson.co.uk>
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
hifive-unleashed-5.1
Dave Gordon 2016-07-13 16:03:35 +01:00 committed by Tvrtko Ursulin
parent 035ea405c9
commit c2c7f24008
3 changed files with 44 additions and 47 deletions
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46
drivers/gpu/drm/i915/intel_lrc.c
View File

@ -1978,8 +1978,9 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
}
static inline void
logical_ring_default_irqs(struct intel_engine_cs *engine, unsigned shift)
logical_ring_default_irqs(struct intel_engine_cs *engine)
{
unsigned shift = engine->irq_shift;
engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift;
engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift;
}
@ -2083,14 +2084,14 @@ static int logical_render_ring_init(struct intel_engine_cs *engine)
return ret;
}
static const struct logical_ring_info {
static const struct engine_info {
const char *name;
unsigned exec_id;
unsigned guc_id;
u32 mmio_base;
unsigned irq_shift;
int (*init)(struct intel_engine_cs *engine);
} logical_rings[] = {
} intel_engines[] = {
[RCS] = {
.name = "render ring",
.exec_id = I915_EXEC_RENDER,
@ -2133,20 +2134,31 @@ static const struct logical_ring_info {
},
};
struct intel_engine_cs *
intel_engine_setup(struct drm_i915_private *dev_priv,
enum intel_engine_id id)
{
const struct engine_info *info = &intel_engines[id];
struct intel_engine_cs *engine = &dev_priv->engine[id];
engine->id = id;
engine->i915 = dev_priv;
engine->name = info->name;
engine->exec_id = info->exec_id;
engine->hw_id = engine->guc_id = info->guc_id;
engine->mmio_base = info->mmio_base;
engine->irq_shift = info->irq_shift;
return engine;
}
static struct intel_engine_cs *
logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id)
{
const struct logical_ring_info *info = &logical_rings[id];
struct intel_engine_cs *engine = &dev_priv->engine[id];
struct intel_engine_cs *engine;
enum forcewake_domains fw_domains;
engine->id = id;
engine->name = info->name;
engine->exec_id = info->exec_id;
engine->guc_id = info->guc_id;
engine->mmio_base = info->mmio_base;
engine->i915 = dev_priv;
engine = intel_engine_setup(dev_priv, id);
/* Intentionally left blank. */
engine->buffer = NULL;
@ -2176,7 +2188,7 @@ logical_ring_setup(struct drm_i915_private *dev_priv, enum intel_engine_id id)
logical_ring_init_platform_invariants(engine);
logical_ring_default_vfuncs(engine);
logical_ring_default_irqs(engine, info->irq_shift);
logical_ring_default_irqs(engine);
intel_engine_init_hangcheck(engine);
i915_gem_batch_pool_init(&dev_priv->drm, &engine->batch_pool);
@ -2205,14 +2217,14 @@ int intel_logical_rings_init(struct drm_device *dev)
WARN_ON(INTEL_INFO(dev_priv)->ring_mask &
GENMASK(sizeof(mask) * BITS_PER_BYTE - 1, I915_NUM_ENGINES));
for (i = 0; i < ARRAY_SIZE(logical_rings); i++) {
for (i = 0; i < ARRAY_SIZE(intel_engines); i++) {
if (!HAS_ENGINE(dev_priv, i))
continue;
if (!logical_rings[i].init)
if (!intel_engines[i].init)
continue;
ret = logical_rings[i].init(logical_ring_setup(dev_priv, i));
ret = intel_engines[i].init(logical_ring_setup(dev_priv, i));
if (ret)
goto cleanup;
@ -2220,7 +2232,7 @@ int intel_logical_rings_init(struct drm_device *dev)
}
/*
* Catch failures to update logical_rings table when the new engines
* Catch failures to update intel_engines table when the new engines
* are added to the driver by a warning and disabling the forgotten
* engines.
*/

40
drivers/gpu/drm/i915/intel_ringbuffer.c
View File

@ -2839,14 +2839,10 @@ static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
int intel_init_render_ring_buffer(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_engine_cs *engine = &dev_priv->engine[RCS];
struct intel_engine_cs *engine;
int ret;
engine->name = "render ring";
engine->id = RCS;
engine->exec_id = I915_EXEC_RENDER;
engine->hw_id = 0;
engine->mmio_base = RENDER_RING_BASE;
engine = intel_engine_setup(dev_priv, RCS);
intel_ring_default_vfuncs(dev_priv, engine);
@ -2901,17 +2897,13 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
int intel_init_bsd_ring_buffer(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_engine_cs *engine = &dev_priv->engine[VCS];
struct intel_engine_cs *engine;
engine->name = "bsd ring";
engine->id = VCS;
engine->exec_id = I915_EXEC_BSD;
engine->hw_id = 1;
engine = intel_engine_setup(dev_priv, VCS);
intel_ring_default_vfuncs(dev_priv, engine);
if (INTEL_GEN(dev_priv) >= 6) {
engine->mmio_base = GEN6_BSD_RING_BASE;
/* gen6 bsd needs a special wa for tail updates */
if (IS_GEN6(dev_priv))
engine->write_tail = gen6_bsd_ring_write_tail;
@ -2939,13 +2931,9 @@ int intel_init_bsd_ring_buffer(struct drm_device *dev)
int intel_init_bsd2_ring_buffer(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_engine_cs *engine = &dev_priv->engine[VCS2];
struct intel_engine_cs *engine;
engine->name = "bsd2 ring";
engine->id = VCS2;
engine->exec_id = I915_EXEC_BSD;
engine->hw_id = 4;
engine->mmio_base = GEN8_BSD2_RING_BASE;
engine = intel_engine_setup(dev_priv, VCS2);
intel_ring_default_vfuncs(dev_priv, engine);
@ -2959,13 +2947,9 @@ int intel_init_bsd2_ring_buffer(struct drm_device *dev)
int intel_init_blt_ring_buffer(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_engine_cs *engine = &dev_priv->engine[BCS];
struct intel_engine_cs *engine;
engine->name = "blitter ring";
engine->id = BCS;
engine->exec_id = I915_EXEC_BLT;
engine->hw_id = 2;
engine->mmio_base = BLT_RING_BASE;
engine = intel_engine_setup(dev_priv, BCS);
intel_ring_default_vfuncs(dev_priv, engine);
@ -2982,13 +2966,9 @@ int intel_init_blt_ring_buffer(struct drm_device *dev)
int intel_init_vebox_ring_buffer(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_engine_cs *engine = &dev_priv->engine[VECS];
struct intel_engine_cs *engine;
engine->name = "video enhancement ring";
engine->id = VECS;
engine->exec_id = I915_EXEC_VEBOX;
engine->hw_id = 3;
engine->mmio_base = VEBOX_RING_BASE;
engine = intel_engine_setup(dev_priv, VECS);
intel_ring_default_vfuncs(dev_priv, engine);

5
drivers/gpu/drm/i915/intel_ringbuffer.h
View File

@ -147,6 +147,7 @@ struct intel_engine_cs {
unsigned int hw_id;
unsigned int guc_id; /* XXX same as hw_id? */
u32 mmio_base;
unsigned int irq_shift;
struct intel_ringbuffer *buffer;
struct list_head buffers;
@ -361,6 +362,10 @@ struct intel_engine_cs {
u32 (*get_cmd_length_mask)(u32 cmd_header);
};
struct intel_engine_cs *
intel_engine_setup(struct drm_i915_private *dev_priv,
enum intel_engine_id id);
static inline bool
intel_engine_initialized(const struct intel_engine_cs *engine)
{