[PATCH] forcedeth: rewritten tx irq handling
This is a multi-part message in MIME format. Signed-off-by: Jeff Garzik <jgarzik@pobox.com>hifive-unleashed-5.1
Manfred Spraul
Jeff Garzik
parent
dc8216c192
commit
c2dba06dae
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@ -87,6 +87,8 @@
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* 0.35: 26 Jun 2005: Support for MCP55 added.
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* 0.36: 28 Jun 2005: Add jumbo frame support.
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* 0.37: 10 Jul 2005: Additional ethtool support, cleanup of pci id list
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* 0.38: 16 Jul 2005: tx irq rewrite: Use global flags instead of
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* per-packet flags.
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*
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* Known bugs:
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* We suspect that on some hardware no TX done interrupts are generated.
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@ -98,7 +100,7 @@
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* DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
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* superfluous timer interrupts from the nic.
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*/
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#define FORCEDETH_VERSION "0.37"
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#define FORCEDETH_VERSION "0.38"
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#define DRV_NAME "forcedeth"
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#include <linux/module.h>
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@ -133,12 +135,9 @@
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* Hardware access:
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*/
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#define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
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#define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
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#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
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#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
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#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
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#define DEV_HAS_LARGEDESC 0x0020 /* device supports jumbo frames and needs packet format 2 */
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#define DEV_NEED_TIMERIRQ 0x0001 /* set the timer irq flag in the irq mask */
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#define DEV_NEED_LINKTIMER 0x0002 /* poll link settings. Relies on the timer irq */
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#define DEV_HAS_LARGEDESC 0x0004 /* device supports jumbo frames and needs packet format 2 */
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enum {
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NvRegIrqStatus = 0x000,
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@ -149,13 +148,16 @@ enum {
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#define NVREG_IRQ_RX 0x0002
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#define NVREG_IRQ_RX_NOBUF 0x0004
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#define NVREG_IRQ_TX_ERR 0x0008
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#define NVREG_IRQ_TX2 0x0010
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#define NVREG_IRQ_TX_OK 0x0010
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#define NVREG_IRQ_TIMER 0x0020
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#define NVREG_IRQ_LINK 0x0040
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#define NVREG_IRQ_TX_ERROR 0x0080
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#define NVREG_IRQ_TX1 0x0100
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#define NVREG_IRQMASK_WANTED_1 0x005f
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#define NVREG_IRQMASK_WANTED_2 0x0147
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#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR|NVREG_IRQ_TX2|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX1))
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#define NVREG_IRQMASK_WANTED 0x00df
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#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \
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NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_TX_ERROR| \
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NVREG_IRQ_TX1))
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NvRegUnknownSetupReg6 = 0x008,
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#define NVREG_UNKSETUP6_VAL 3
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@ -296,7 +298,7 @@ struct ring_desc {
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#define NV_TX_LASTPACKET (1<<16)
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#define NV_TX_RETRYERROR (1<<19)
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#define NV_TX_LASTPACKET1 (1<<24)
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#define NV_TX_FORCED_INTERRUPT (1<<24)
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#define NV_TX_DEFERRED (1<<26)
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#define NV_TX_CARRIERLOST (1<<27)
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#define NV_TX_LATECOLLISION (1<<28)
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@ -306,7 +308,7 @@ struct ring_desc {
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#define NV_TX2_LASTPACKET (1<<29)
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#define NV_TX2_RETRYERROR (1<<18)
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#define NV_TX2_LASTPACKET1 (1<<23)
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#define NV_TX2_FORCED_INTERRUPT (1<<30)
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#define NV_TX2_DEFERRED (1<<25)
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#define NV_TX2_CARRIERLOST (1<<26)
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#define NV_TX2_LATECOLLISION (1<<27)
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@ -1013,9 +1015,39 @@ static void nv_tx_timeout(struct net_device *dev)
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struct fe_priv *np = get_nvpriv(dev);
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u8 __iomem *base = get_hwbase(dev);
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dprintk(KERN_DEBUG "%s: Got tx_timeout. irq: %08x\n", dev->name,
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printk(KERN_INFO "%s: Got tx_timeout. irq: %08x\n", dev->name,
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readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK);
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{
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int i;
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printk(KERN_INFO "%s: Ring at %lx: next %d nic %d\n",
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dev->name, (unsigned long)np->ring_addr,
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np->next_tx, np->nic_tx);
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printk(KERN_INFO "%s: Dumping tx registers\n", dev->name);
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for (i=0;i<0x400;i+= 32) {
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printk(KERN_INFO "%3x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
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i,
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readl(base + i + 0), readl(base + i + 4),
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readl(base + i + 8), readl(base + i + 12),
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readl(base + i + 16), readl(base + i + 20),
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readl(base + i + 24), readl(base + i + 28));
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}
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printk(KERN_INFO "%s: Dumping tx ring\n", dev->name);
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for (i=0;i<TX_RING;i+= 4) {
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printk(KERN_INFO "%03x: %08x %08x // %08x %08x // %08x %08x // %08x %08x\n",
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i,
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le32_to_cpu(np->tx_ring[i].PacketBuffer),
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le32_to_cpu(np->tx_ring[i].FlagLen),
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le32_to_cpu(np->tx_ring[i+1].PacketBuffer),
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le32_to_cpu(np->tx_ring[i+1].FlagLen),
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le32_to_cpu(np->tx_ring[i+2].PacketBuffer),
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le32_to_cpu(np->tx_ring[i+2].FlagLen),
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le32_to_cpu(np->tx_ring[i+3].PacketBuffer),
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le32_to_cpu(np->tx_ring[i+3].FlagLen));
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}
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}
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spin_lock_irq(&np->lock);
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/* 1) stop tx engine */
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@ -1557,7 +1589,7 @@ static irqreturn_t nv_nic_irq(int foo, void *data, struct pt_regs *regs)
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if (!(events & np->irqmask))
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break;
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if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX2|NVREG_IRQ_TX_ERR)) {
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if (events & (NVREG_IRQ_TX1|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_ERROR|NVREG_IRQ_TX_ERR)) {
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spin_lock(&np->lock);
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nv_tx_done(dev);
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spin_unlock(&np->lock);
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@ -2213,17 +2245,10 @@ static int __devinit nv_probe(struct pci_dev *pci_dev, const struct pci_device_i
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if (np->desc_ver == DESC_VER_1) {
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np->tx_flags = NV_TX_LASTPACKET|NV_TX_VALID;
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if (id->driver_data & DEV_NEED_LASTPACKET1)
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np->tx_flags |= NV_TX_LASTPACKET1;
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} else {
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np->tx_flags = NV_TX2_LASTPACKET|NV_TX2_VALID;
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if (id->driver_data & DEV_NEED_LASTPACKET1)
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np->tx_flags |= NV_TX2_LASTPACKET1;
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}
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if (id->driver_data & DEV_IRQMASK_1)
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np->irqmask = NVREG_IRQMASK_WANTED_1;
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if (id->driver_data & DEV_IRQMASK_2)
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np->irqmask = NVREG_IRQMASK_WANTED_2;
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np->irqmask = NVREG_IRQMASK_WANTED;
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if (id->driver_data & DEV_NEED_TIMERIRQ)
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np->irqmask |= NVREG_IRQ_TIMER;
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if (id->driver_data & DEV_NEED_LINKTIMER) {
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@ -2329,73 +2354,63 @@ static void __devexit nv_remove(struct pci_dev *pci_dev)
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static struct pci_device_id pci_tbl[] = {
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{ /* nForce Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_1),
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.driver_data = DEV_IRQMASK_1|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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},
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{ /* nForce2 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_2),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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},
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{ /* nForce3 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_3),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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},
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{ /* nForce3 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_4),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* nForce3 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_5),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* nForce3 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_6),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* nForce3 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_7),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* CK804 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_8),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* CK804 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_9),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* MCP04 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_10),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* MCP04 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_11),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* MCP51 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_12),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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},
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{ /* MCP51 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_13),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
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},
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{ /* MCP55 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_14),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{ /* MCP55 Ethernet Controller */
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PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NVENET_15),
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.driver_data = DEV_NEED_LASTPACKET1|DEV_IRQMASK_2|DEV_NEED_TIMERIRQ|
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DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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.driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC,
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},
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{0,},
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};
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