ARM: tegra: clock: Fix clock issues in suspend
The PLLP registers are now being restored by the low-level resume code, and the CPU may be running off PLLP, so don't touch them during clock resume. Save plld, plls, pllu, and audio clock during suspend (originally fixed by Mayuresh Kulkarni <mkulkarni@nvidia.com>) The lock time for plld is 1000 us, so increase the delay after setting the PLLs. Add a BUG_ON to ensure the size of the suspend context area is correct. Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Colin Cross <ccross@android.com>
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@ -2236,7 +2236,7 @@ void __init tegra2_init_clocks(void)
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#ifdef CONFIG_PM
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static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
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PERIPH_CLK_SOURCE_NUM + 19];
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PERIPH_CLK_SOURCE_NUM + 22];
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void tegra_clk_suspend(void)
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{
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@ -2244,16 +2244,18 @@ void tegra_clk_suspend(void)
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u32 *ctx = clk_rst_suspend;
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*ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
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*ctx++ = clk_readl(tegra_pll_p.reg + PLL_BASE);
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*ctx++ = clk_readl(tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
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*ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
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*ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
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*ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
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*ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
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*ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
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*ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
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*ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
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*ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
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*ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
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*ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
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*ctx++ = clk_readl(tegra_pll_m_out1.reg);
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*ctx++ = clk_readl(tegra_pll_p_out1.reg);
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*ctx++ = clk_readl(tegra_pll_p_out3.reg);
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*ctx++ = clk_readl(tegra_pll_a_out0.reg);
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*ctx++ = clk_readl(tegra_pll_c_out1.reg);
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@ -2264,6 +2266,8 @@ void tegra_clk_suspend(void)
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*ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
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*ctx++ = clk_readl(tegra_clk_pclk.reg);
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*ctx++ = clk_readl(tegra_clk_audio.reg);
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for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
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off += 4) {
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if (off == PERIPH_CLK_SOURCE_EMC)
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@ -2281,6 +2285,8 @@ void tegra_clk_suspend(void)
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*ctx++ = clk_readl(MISC_CLK_ENB);
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*ctx++ = clk_readl(CLK_MASK_ARM);
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BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
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}
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void tegra_clk_resume(void)
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@ -2293,17 +2299,19 @@ void tegra_clk_resume(void)
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val |= *ctx++;
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clk_writel(val, OSC_CTRL);
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clk_writel(*ctx++, tegra_pll_p.reg + PLL_BASE);
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clk_writel(*ctx++, tegra_pll_p.reg + PLL_MISC(&tegra_pll_p));
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clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
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clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
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clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
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clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
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udelay(300);
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clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
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clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
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clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
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clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
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clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
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clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
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udelay(1000);
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clk_writel(*ctx++, tegra_pll_m_out1.reg);
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clk_writel(*ctx++, tegra_pll_p_out1.reg);
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clk_writel(*ctx++, tegra_pll_p_out3.reg);
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clk_writel(*ctx++, tegra_pll_a_out0.reg);
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clk_writel(*ctx++, tegra_pll_c_out1.reg);
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@ -2314,6 +2322,8 @@ void tegra_clk_resume(void)
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clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
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clk_writel(*ctx++, tegra_clk_pclk.reg);
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clk_writel(*ctx++, tegra_clk_audio.reg);
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/* enable all clocks before configuring clock sources */
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clk_writel(0xbffffff9ul, CLK_OUT_ENB);
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clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
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