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staging/lustre/llite: to configure max_cached_mb correctly 

If there exists MGS conf_param to reduce the memory cache
max_cached_mb it will fail because dt_exp is not initialized
yet.

It should just go ahead and configure it because certainly it
have enough free LRU slot to deduct ccc_lru_left.

Signed-off-by: Jinshan Xiong <jinshan.xiong@intel.com>
Reviewed-on: http://review.whamcloud.com/11783
Intel-bug-id: https://jira.hpdd.intel.com/browse/LU-3676
Reviewed-by: Bobi Jam <bobijam@gmail.com>
Reviewed-by: Andreas Dilger <andreas.dilger@intel.com>
Signed-off-by: Oleg Drokin <oleg.drokin@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
hifive-unleashed-5.1
Jinshan Xiong 2015-02-01 21:52:07 -05:00 committed by Greg Kroah-Hartman
parent af3fa7c71b
commit c2fcdf6c42
1 changed files with 5 additions and 3 deletions
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8
drivers/staging/lustre/lustre/llite/lproc_llite.c
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@ -399,9 +399,6 @@ static ssize_t ll_max_cached_mb_seq_write(struct file *file,
return -ERANGE;
}
if (sbi->ll_dt_exp == NULL)
return -ENODEV;
spin_lock(&sbi->ll_lock);
diff = pages_number - cache->ccc_lru_max;
spin_unlock(&sbi->ll_lock);
@ -437,6 +434,11 @@ static ssize_t ll_max_cached_mb_seq_write(struct file *file,
if (diff <= 0)
break;
if (sbi->ll_dt_exp == NULL) { /* being initialized */
rc = -ENODEV;
break;
}
/* difficult - have to ask OSCs to drop LRU slots. */
tmp = diff << 1;
rc = obd_set_info_async(NULL, sbi->ll_dt_exp,