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drm/amdgpu/atom: add support for new div32 opcodes (v3) 

Better precision than the regular div opcode.

v2: drop 64 bit divide
v3: fix op handling.  This actually is a 64 bit divide.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
hifive-unleashed-5.1
Alex Deucher 2015-10-02 14:26:41 -04:00
parent c9c145021f
commit c2fe16aa36
2 changed files with 25 additions and 2 deletions
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25
drivers/gpu/drm/amd/amdgpu/atom.c
View File

@ -685,6 +685,27 @@ static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
}
}
static void atom_op_div32(atom_exec_context *ctx, int *ptr, int arg)
{
uint64_t val64;
uint8_t attr = U8((*ptr)++);
uint32_t dst, src;
SDEBUG(" src1: ");
dst = atom_get_dst(ctx, arg, attr, ptr, NULL, 1);
SDEBUG(" src2: ");
src = atom_get_src(ctx, attr, ptr);
if (src != 0) {
val64 = dst;
val64 |= ((uint64_t)ctx->ctx->divmul[1]) << 32;
do_div(val64, src);
ctx->ctx->divmul[0] = lower_32_bits(val64);
ctx->ctx->divmul[1] = upper_32_bits(val64);
} else {
ctx->ctx->divmul[0] = 0;
ctx->ctx->divmul[1] = 0;
}
}
static void atom_op_eot(atom_exec_context *ctx, int *ptr, int arg)
{
/* functionally, a nop */
@ -1176,7 +1197,9 @@ static struct {
atom_op_debug, 0}, {
atom_op_processds, 0}, {
atom_op_mul32, ATOM_ARG_PS}, {
atom_op_mul32, ATOM_ARG_WS},
atom_op_mul32, ATOM_ARG_WS}, {
atom_op_div32, ATOM_ARG_PS}, {
atom_op_div32, ATOM_ARG_WS},
};
static int amdgpu_atom_execute_table_locked(struct atom_context *ctx, int index, uint32_t * params)

2
drivers/gpu/drm/amd/amdgpu/atom.h
View File

@ -60,7 +60,7 @@
#define ATOM_CT_PS_MASK 0x7F
#define ATOM_CT_CODE_PTR 6
#define ATOM_OP_CNT 125
#define ATOM_OP_CNT 127
#define ATOM_OP_EOT 91
#define ATOM_CASE_MAGIC 0x63