MLK-21509-1 gpu: imx: dpu: common: Add signature unit support
This patch adds signature unit support in the dpu common driver. Signed-off-by: Liu Ying <victor.liu@nxp.com> Reviewed-by: Robby Cai <robby.cai@nxp.com>5.4-rM2-2.2.x-imx-squashed
Liu Ying
parent
97b5de8b94
commit
c30b395e8d
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@ -4,4 +4,5 @@ imx-dpu-core-objs := dpu-common.o dpu-constframe.o dpu-disengcfg.o \
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dpu-extdst.o dpu-fetchdecode.o dpu-fetcheco.o \
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dpu-fetchlayer.o dpu-fetchwarp.o dpu-fetchunit.o \
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dpu-framegen.o dpu-hscaler.o dpu-layerblend.o \
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dpu-sc-misc.o dpu-store.o dpu-tcon.o dpu-vscaler.o
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dpu-sc-misc.o dpu-signature.o dpu-store.o dpu-tcon.o \
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dpu-vscaler.o
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@ -111,6 +111,9 @@ static const unsigned long hs_pec_ofss[] = {0xb00, 0xb60, 0x8c0};
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static const unsigned long lb_ofss[] = {0xa400, 0xa800, 0xac00, 0xb000};
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static const unsigned long lb_pec_ofss[] = {0xba0, 0xbc0, 0xbe0, 0xc00};
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/* Signature Unit */
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static const unsigned long sig_ofss[] = {0xd000, 0xec00};
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/* Store Unit */
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static const unsigned long st_ofss[] = {0x4000};
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static const unsigned long st_pec_ofss[] = {0x940};
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@ -205,6 +208,14 @@ static const struct dpu_unit _lbs = {
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.ofss = lb_ofss,
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};
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static const struct dpu_unit _sigs = {
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.name = "Signature",
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.num = ARRAY_SIZE(sig_ids),
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.ids = sig_ids,
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.pec_ofss = NULL,
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.ofss = sig_ofss,
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};
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static const struct dpu_unit _sts = {
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.name = "Store",
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.num = ARRAY_SIZE(st_ids),
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@ -259,6 +270,7 @@ static const struct dpu_data dpu_data_qxp = {
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.fws = &_fws,
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.hss = &_hss,
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.lbs = &_lbs,
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.sigs = &_sigs,
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.sts = &_sts,
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.tcons = &_tcons,
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.vss = &_vss,
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@ -283,6 +295,7 @@ static const struct dpu_data dpu_data_qm = {
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.fws = &_fws,
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.hss = &_hss,
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.lbs = &_lbs,
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.sigs = &_sigs,
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.sts = &_sts,
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.tcons = &_tcons,
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.vss = &_vss,
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@ -540,6 +553,7 @@ static void dpu_units_addr_dbg(struct dpu_soc *dpu,
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DPU_UNITS_ADDR_DBG(fw);
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DPU_UNITS_ADDR_DBG(hs);
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DPU_UNITS_ADDR_DBG(lb);
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DPU_UNITS_ADDR_DBG(sig);
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DPU_UNITS_ADDR_DBG(st);
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DPU_UNITS_ADDR_DBG(tcon);
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DPU_UNITS_ADDR_DBG(vs);
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@ -563,8 +577,12 @@ static int dpu_get_irq(struct platform_device *pdev, struct dpu_soc *dpu)
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DPU_GET_IRQ(extdst5_shdload);
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DPU_GET_IRQ(disengcfg_shdload0);
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DPU_GET_IRQ(disengcfg_framecomplete0);
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DPU_GET_IRQ(sig0_shdload);
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DPU_GET_IRQ(sig0_valid);
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DPU_GET_IRQ(disengcfg_shdload1);
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DPU_GET_IRQ(disengcfg_framecomplete1);
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DPU_GET_IRQ(sig1_shdload);
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DPU_GET_IRQ(sig1_valid);
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return 0;
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}
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@ -604,8 +622,12 @@ DPU_IRQ_HANDLER_DEFINE(extdst1_shdload, EXTDST1_SHDLOAD)
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DPU_IRQ_HANDLER_DEFINE(extdst5_shdload, EXTDST5_SHDLOAD)
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DPU_IRQ_HANDLER_DEFINE(disengcfg_shdload0, DISENGCFG_SHDLOAD0)
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DPU_IRQ_HANDLER_DEFINE(disengcfg_framecomplete0, DISENGCFG_FRAMECOMPLETE0)
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DPU_IRQ_HANDLER_DEFINE(sig0_shdload, SIG0_SHDLOAD);
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DPU_IRQ_HANDLER_DEFINE(sig0_valid, SIG0_VALID);
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DPU_IRQ_HANDLER_DEFINE(disengcfg_shdload1, DISENGCFG_SHDLOAD1)
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DPU_IRQ_HANDLER_DEFINE(disengcfg_framecomplete1, DISENGCFG_FRAMECOMPLETE1)
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DPU_IRQ_HANDLER_DEFINE(sig1_shdload, SIG1_SHDLOAD);
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DPU_IRQ_HANDLER_DEFINE(sig1_valid, SIG1_VALID);
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int dpu_map_irq(struct dpu_soc *dpu, int irq)
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{
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@ -675,8 +697,12 @@ irq_set_chained_handler_and_data(dpu->irq_##name, dpu_##name##_irq_handler, dpu)
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(extdst5_shdload);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(disengcfg_shdload0);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(disengcfg_framecomplete0);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(sig0_shdload);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(sig0_valid);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(disengcfg_shdload1);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(disengcfg_framecomplete1);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(sig1_shdload);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA1(sig1_valid);
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#define DPU_IRQ_CHIP_PM_GET(name) \
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{ \
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@ -704,8 +730,12 @@ irq_set_chained_handler_and_data(dpu->irq_##name, dpu_##name##_irq_handler, dpu)
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DPU_IRQ_CHIP_PM_GET(extdst5_shdload);
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DPU_IRQ_CHIP_PM_GET(disengcfg_shdload0);
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DPU_IRQ_CHIP_PM_GET(disengcfg_framecomplete0);
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DPU_IRQ_CHIP_PM_GET(sig0_shdload);
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DPU_IRQ_CHIP_PM_GET(sig0_valid);
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DPU_IRQ_CHIP_PM_GET(disengcfg_shdload1);
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DPU_IRQ_CHIP_PM_GET(disengcfg_framecomplete1);
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DPU_IRQ_CHIP_PM_GET(sig1_shdload);
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DPU_IRQ_CHIP_PM_GET(sig1_valid);
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return 0;
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@ -716,8 +746,12 @@ pm_get_rollback:
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DPU_IRQ_CHIP_PM_PUT_CHECK(extdst5_shdload);
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DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_shdload0);
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DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_framecomplete0);
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DPU_IRQ_CHIP_PM_PUT_CHECK(sig0_shdload);
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DPU_IRQ_CHIP_PM_PUT_CHECK(sig0_valid);
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DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_shdload1);
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DPU_IRQ_CHIP_PM_PUT_CHECK(disengcfg_framecomplete1);
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DPU_IRQ_CHIP_PM_PUT_CHECK(sig1_shdload);
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DPU_IRQ_CHIP_PM_PUT_CHECK(sig1_valid);
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return ret;
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}
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@ -738,8 +772,12 @@ static void dpu_irq_exit(struct dpu_soc *dpu)
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DPU_IRQ_CHIP_PM_PUT(extdst5_shdload);
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DPU_IRQ_CHIP_PM_PUT(disengcfg_shdload0);
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DPU_IRQ_CHIP_PM_PUT(disengcfg_framecomplete0);
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DPU_IRQ_CHIP_PM_PUT(sig0_shdload);
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DPU_IRQ_CHIP_PM_PUT(sig0_valid);
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DPU_IRQ_CHIP_PM_PUT(disengcfg_shdload1);
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DPU_IRQ_CHIP_PM_PUT(disengcfg_framecomplete1);
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DPU_IRQ_CHIP_PM_PUT(sig1_shdload);
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DPU_IRQ_CHIP_PM_PUT(sig1_valid);
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#define DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(name) \
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irq_set_chained_handler_and_data(dpu->irq_##name, NULL, NULL)
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@ -750,8 +788,12 @@ irq_set_chained_handler_and_data(dpu->irq_##name, NULL, NULL)
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(extdst5_shdload);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(disengcfg_shdload0);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(disengcfg_framecomplete0);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(sig0_shdload);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(sig0_valid);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(disengcfg_shdload1);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(disengcfg_framecomplete1);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(sig1_shdload);
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DPU_IRQ_SET_CHAINED_HANDLER_AND_DATA2(sig1_valid);
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for (i = 0; i < dpu->irq_line_num; i++) {
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irq = irq_linear_revmap(dpu->domain, i);
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@ -790,6 +832,7 @@ _dpu_submodules_init(struct dpu_soc *dpu, struct platform_device *pdev)
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_DPU_UNITS_INIT(fw);
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_DPU_UNITS_INIT(hs);
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_DPU_UNITS_INIT(lb);
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_DPU_UNITS_INIT(sig);
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_DPU_UNITS_INIT(st);
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_DPU_UNITS_INIT(tcon);
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_DPU_UNITS_INIT(vs);
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@ -850,6 +893,7 @@ static int dpu_submodules_init(struct dpu_soc *dpu,
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DPU_UNITS_INIT(fw);
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DPU_UNITS_INIT(hs);
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DPU_UNITS_INIT(lb);
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DPU_UNITS_INIT(sig);
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DPU_UNITS_INIT(st);
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DPU_UNITS_INIT(tcon);
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DPU_UNITS_INIT(vs);
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@ -194,6 +194,7 @@ struct dpu_data {
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const struct dpu_unit *fws;
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const struct dpu_unit *hss;
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const struct dpu_unit *lbs;
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const struct dpu_unit *sigs;
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const struct dpu_unit *sts;
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const struct dpu_unit *tcons;
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const struct dpu_unit *vss;
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@ -233,8 +234,12 @@ struct dpu_soc {
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int irq_extdst5_shdload;
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int irq_disengcfg_shdload0;
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int irq_disengcfg_framecomplete0;
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int irq_sig0_shdload;
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int irq_sig0_valid;
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int irq_disengcfg_shdload1;
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int irq_disengcfg_framecomplete1;
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int irq_sig1_shdload;
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int irq_sig1_valid;
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int irq_line_num;
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bool irq_chip_pm_get_extdst0_shdload;
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@ -243,8 +248,12 @@ struct dpu_soc {
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bool irq_chip_pm_get_extdst5_shdload;
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bool irq_chip_pm_get_disengcfg_shdload0;
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bool irq_chip_pm_get_disengcfg_framecomplete0;
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bool irq_chip_pm_get_sig0_shdload;
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bool irq_chip_pm_get_sig0_valid;
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bool irq_chip_pm_get_disengcfg_shdload1;
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bool irq_chip_pm_get_disengcfg_framecomplete1;
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bool irq_chip_pm_get_sig1_shdload;
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bool irq_chip_pm_get_sig1_valid;
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struct irq_domain *domain;
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@ -260,6 +269,7 @@ struct dpu_soc {
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struct dpu_fetchunit *fw_priv[1];
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struct dpu_hscaler *hs_priv[3];
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struct dpu_layerblend *lb_priv[4];
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struct dpu_signature *sig_priv[2];
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struct dpu_store *st_priv[1];
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struct dpu_tcon *tcon_priv[2];
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struct dpu_vscaler *vs_priv[3];
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@ -284,6 +294,7 @@ _DECLARE_DPU_UNIT_INIT_FUNC(fl);
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_DECLARE_DPU_UNIT_INIT_FUNC(fw);
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_DECLARE_DPU_UNIT_INIT_FUNC(hs);
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_DECLARE_DPU_UNIT_INIT_FUNC(lb);
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_DECLARE_DPU_UNIT_INIT_FUNC(sig);
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_DECLARE_DPU_UNIT_INIT_FUNC(st);
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_DECLARE_DPU_UNIT_INIT_FUNC(tcon);
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_DECLARE_DPU_UNIT_INIT_FUNC(vs);
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@ -302,6 +313,7 @@ DECLARE_DPU_UNIT_INIT_FUNC(fl);
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DECLARE_DPU_UNIT_INIT_FUNC(fw);
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DECLARE_DPU_UNIT_INIT_FUNC(hs);
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DECLARE_DPU_UNIT_INIT_FUNC(lb);
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DECLARE_DPU_UNIT_INIT_FUNC(sig);
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DECLARE_DPU_UNIT_INIT_FUNC(st);
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DECLARE_DPU_UNIT_INIT_FUNC(tcon);
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DECLARE_DPU_UNIT_INIT_FUNC(vs);
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@ -350,6 +362,7 @@ static const unsigned int fl_ids[] = {0};
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static const unsigned int fw_ids[] = {2};
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static const unsigned int hs_ids[] = {4, 5, 9};
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static const unsigned int lb_ids[] = {0, 1, 2, 3};
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static const unsigned int sig_ids[] = {0, 1};
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static const unsigned int st_ids[] = {9};
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static const unsigned int tcon_ids[] = {0, 1};
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static const unsigned int vs_ids[] = {4, 5, 9};
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@ -0,0 +1,392 @@
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/*
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* Copyright 2019,2020 NXP
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mutex.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include "dpu-prv.h"
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#define STATICCONTROL 0x8
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#define SHDLDSEL BIT(4)
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#define LOCAL 0
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#define GLOBAL BIT(4)
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#define PANICCOLOR 0xC
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#define EVALCONTRL(n) (0x10 + (n) * 0x24)
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#define ENGLOBALPANIC BIT(17)
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#define ENLOCALPANIC BIT(16)
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#define ALPHAINV BIT(9)
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#define ALPHAMASK BIT(8)
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#define ENCRC BIT(1)
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#define ENEVALWIN BIT(0)
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#define EVALUPPERLEFT(n) (0x14 + (n) * 0x24)
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#define EVALLOWERRIGHT(n) (0x18 + (n) * 0x24)
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#define YEVAL(y) (((y) & 0x3FFF) << 16)
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#define XEVAL(x) ((x) & 0x3FFF)
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#define SIGCRCREDREF(n) (0x1C + (n) * 0x24)
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#define SIGCRCGREENREF(n) (0x20 + (n) * 0x24)
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#define SIGCRCBLUEREF(n) (0x24 + (n) * 0x24)
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#define SIGCRCRED(n) (0x28 + (n) * 0x24)
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#define SIGCRCGREEN(n) (0x2C + (n) * 0x24)
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#define SIGCRCBLUE(n) (0x30 + (n) * 0x24)
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#define SHADOWLOAD 0x130
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#define SHDLDREQ(n) BIT(n)
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#define CONTINUOUSMODE 0x134
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#define ENCONT BIT(0)
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#define SOFTWAREKICK 0x138
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#define KICK BIT(0)
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#define STATUS 0x13C
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#define STSSIGIDLE BIT(20)
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#define STSSIGVALID BIT(16)
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#define STSSIGERROR(n) BIT(n)
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#define STSSIGERROR_MASK 0xFF
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struct dpu_signature {
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void __iomem *base;
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struct mutex mutex;
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int id;
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bool inuse;
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struct dpu_soc *dpu;
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};
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static inline u32 dpu_sig_read(struct dpu_signature *sig, unsigned int offset)
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{
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return readl(sig->base + offset);
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}
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static inline void dpu_sig_write(struct dpu_signature *sig,
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unsigned int offset, u32 value)
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{
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writel(value, sig->base + offset);
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}
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void signature_shden(struct dpu_signature *sig, bool enable)
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{
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u32 val;
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mutex_lock(&sig->mutex);
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val = dpu_sig_read(sig, STATICCONTROL);
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if (enable)
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val |= SHDEN;
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else
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val &= ~SHDEN;
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dpu_sig_write(sig, STATICCONTROL, val);
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mutex_unlock(&sig->mutex);
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}
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EXPORT_SYMBOL_GPL(signature_shden);
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void signature_shdldsel_local(struct dpu_signature *sig)
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{
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u32 val;
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mutex_lock(&sig->mutex);
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val = dpu_sig_read(sig, STATICCONTROL);
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val &= ~GLOBAL;
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dpu_sig_write(sig, STATICCONTROL, val);
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mutex_unlock(&sig->mutex);
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}
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EXPORT_SYMBOL_GPL(signature_shdldsel_local);
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void signature_shdldsel_global(struct dpu_signature *sig)
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{
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u32 val;
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mutex_lock(&sig->mutex);
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val = dpu_sig_read(sig, STATICCONTROL);
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dpu_sig_write(sig, STATICCONTROL, val | GLOBAL);
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mutex_unlock(&sig->mutex);
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}
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EXPORT_SYMBOL_GPL(signature_shdldsel_global);
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void
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signature_global_panic(struct dpu_signature *sig, unsigned int win, bool enable)
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{
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u32 val;
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mutex_lock(&sig->mutex);
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val = dpu_sig_read(sig, EVALCONTRL(win));
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if (enable)
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val |= ENGLOBALPANIC;
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else
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val &= ~ENGLOBALPANIC;
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dpu_sig_write(sig, EVALCONTRL(win), val);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_global_panic);
|
||||
|
||||
void
|
||||
signature_local_panic(struct dpu_signature *sig, unsigned int win, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, EVALCONTRL(win));
|
||||
if (enable)
|
||||
val |= ENLOCALPANIC;
|
||||
else
|
||||
val &= ~ENLOCALPANIC;
|
||||
dpu_sig_write(sig, EVALCONTRL(win), val);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_local_panic);
|
||||
|
||||
void
|
||||
signature_alpha_mask(struct dpu_signature *sig, unsigned int win, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, EVALCONTRL(win));
|
||||
if (enable)
|
||||
val |= ALPHAMASK;
|
||||
else
|
||||
val &= ~ALPHAMASK;
|
||||
dpu_sig_write(sig, EVALCONTRL(win), val);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_alpha_mask);
|
||||
|
||||
void signature_crc(struct dpu_signature *sig, unsigned int win, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, EVALCONTRL(win));
|
||||
if (enable)
|
||||
val |= ENCRC;
|
||||
else
|
||||
val &= ~ENCRC;
|
||||
dpu_sig_write(sig, EVALCONTRL(win), val);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_crc);
|
||||
|
||||
void
|
||||
signature_eval_win(struct dpu_signature *sig, unsigned int win, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, EVALCONTRL(win));
|
||||
if (enable)
|
||||
val |= ENEVALWIN;
|
||||
else
|
||||
val &= ~ENEVALWIN;
|
||||
dpu_sig_write(sig, EVALCONTRL(win), val);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_eval_win);
|
||||
|
||||
void signature_win(struct dpu_signature *sig, unsigned int win,
|
||||
int xul, int yul, int xlr, int ylr)
|
||||
{
|
||||
mutex_lock(&sig->mutex);
|
||||
dpu_sig_write(sig, EVALUPPERLEFT(win), XEVAL(xul) | YEVAL(yul));
|
||||
dpu_sig_write(sig, EVALLOWERRIGHT(win), XEVAL(--xlr) | YEVAL(--ylr));
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_win);
|
||||
|
||||
void signature_crc_value(struct dpu_signature *sig, unsigned int win,
|
||||
u32 *red, u32 *green, u32 *blue)
|
||||
{
|
||||
mutex_lock(&sig->mutex);
|
||||
*red = dpu_sig_read(sig, SIGCRCRED(win));
|
||||
*green = dpu_sig_read(sig, SIGCRCGREEN(win));
|
||||
*blue = dpu_sig_read(sig, SIGCRCBLUE(win));
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_crc_value);
|
||||
|
||||
void signature_shdldreq(struct dpu_signature *sig, u8 win_mask)
|
||||
{
|
||||
mutex_lock(&sig->mutex);
|
||||
dpu_sig_write(sig, SHADOWLOAD, win_mask);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_shdldreq);
|
||||
|
||||
void signature_continuous_mode(struct dpu_signature *sig, bool enable)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, CONTINUOUSMODE);
|
||||
if (enable)
|
||||
val |= ENCONT;
|
||||
else
|
||||
val &= ~ENCONT;
|
||||
dpu_sig_write(sig, CONTINUOUSMODE, val);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_continuous_mode);
|
||||
|
||||
void signature_kick(struct dpu_signature *sig)
|
||||
{
|
||||
mutex_lock(&sig->mutex);
|
||||
dpu_sig_write(sig, SOFTWAREKICK, KICK);
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_kick);
|
||||
|
||||
bool signature_is_idle(struct dpu_signature *sig)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, STATUS);
|
||||
mutex_unlock(&sig->mutex);
|
||||
|
||||
return !!(val & STSSIGIDLE);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_is_idle);
|
||||
|
||||
void signature_wait_for_idle(struct dpu_signature *sig)
|
||||
{
|
||||
unsigned long timeout = jiffies + msecs_to_jiffies(100);
|
||||
bool idle;
|
||||
|
||||
do {
|
||||
idle = signature_is_idle(sig);
|
||||
} while (!idle && time_before(jiffies, timeout));
|
||||
|
||||
if (idle)
|
||||
dev_dbg(sig->dpu->dev, "Signature%d is idle\n", sig->id);
|
||||
else
|
||||
dev_err(sig->dpu->dev,
|
||||
"failed to wait for Signature%d idle\n", sig->id);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_wait_for_idle);
|
||||
|
||||
bool signature_is_valid(struct dpu_signature *sig)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, STATUS);
|
||||
mutex_unlock(&sig->mutex);
|
||||
|
||||
return !!(val & STSSIGVALID);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_is_valid);
|
||||
|
||||
bool signature_is_error(struct dpu_signature *sig, u8 *err_win_mask)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
val = dpu_sig_read(sig, STATUS);
|
||||
mutex_unlock(&sig->mutex);
|
||||
|
||||
*err_win_mask = val & STSSIGERROR_MASK;
|
||||
|
||||
return !!(*err_win_mask);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(signature_is_error);
|
||||
|
||||
struct dpu_signature *dpu_sig_get(struct dpu_soc *dpu, int id)
|
||||
{
|
||||
struct dpu_signature *sig;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sig_ids); i++)
|
||||
if (sig_ids[i] == id)
|
||||
break;
|
||||
|
||||
if (i == ARRAY_SIZE(sig_ids))
|
||||
return ERR_PTR(-EINVAL);
|
||||
|
||||
sig = dpu->sig_priv[i];
|
||||
|
||||
mutex_lock(&sig->mutex);
|
||||
|
||||
if (sig->inuse) {
|
||||
mutex_unlock(&sig->mutex);
|
||||
return ERR_PTR(-EBUSY);
|
||||
}
|
||||
|
||||
sig->inuse = true;
|
||||
|
||||
mutex_unlock(&sig->mutex);
|
||||
|
||||
return sig;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dpu_sig_get);
|
||||
|
||||
void dpu_sig_put(struct dpu_signature *sig)
|
||||
{
|
||||
mutex_lock(&sig->mutex);
|
||||
|
||||
sig->inuse = false;
|
||||
|
||||
mutex_unlock(&sig->mutex);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dpu_sig_put);
|
||||
|
||||
struct dpu_signature *dpu_aux_sig_peek(struct dpu_signature *sig)
|
||||
{
|
||||
return sig->dpu->sig_priv[sig->id ^ 1];
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(dpu_aux_sig_peek);
|
||||
|
||||
void _dpu_sig_init(struct dpu_soc *dpu, unsigned int id)
|
||||
{
|
||||
struct dpu_signature *sig;
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sig_ids); i++)
|
||||
if (sig_ids[i] == id)
|
||||
break;
|
||||
|
||||
if (WARN_ON(i == ARRAY_SIZE(sig_ids)))
|
||||
return;
|
||||
|
||||
sig = dpu->sig_priv[i];
|
||||
|
||||
signature_shden(sig, true);
|
||||
signature_shdldsel_local(sig);
|
||||
for (j = 0; j < MAX_DPU_SIGNATURE_WIN_NUM; j++) {
|
||||
signature_global_panic(sig, j, false);
|
||||
signature_local_panic(sig, j, false);
|
||||
signature_alpha_mask(sig, j, false);
|
||||
signature_crc(sig, j, false);
|
||||
signature_eval_win(sig, j, false);
|
||||
signature_continuous_mode(sig, false);
|
||||
}
|
||||
}
|
||||
|
||||
int dpu_sig_init(struct dpu_soc *dpu, unsigned int id,
|
||||
unsigned long unused, unsigned long base)
|
||||
{
|
||||
struct dpu_signature *sig;
|
||||
|
||||
sig = devm_kzalloc(dpu->dev, sizeof(*sig), GFP_KERNEL);
|
||||
if (!sig)
|
||||
return -ENOMEM;
|
||||
|
||||
dpu->sig_priv[id] = sig;
|
||||
|
||||
sig->base = devm_ioremap(dpu->dev, base, SZ_512);
|
||||
if (!sig->base)
|
||||
return -ENOMEM;
|
||||
|
||||
sig->dpu = dpu;
|
||||
sig->id = id;
|
||||
mutex_init(&sig->mutex);
|
||||
|
||||
_dpu_sig_init(dpu, id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/*
|
||||
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017-2019 NXP
|
||||
* Copyright 2017-2020 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
|
|
@ -325,6 +325,11 @@ enum {
|
|||
FU_T_FW,
|
||||
};
|
||||
|
||||
enum dpu_crc_source {
|
||||
DPU_CRC_SRC_NONE,
|
||||
DPU_CRC_SRC_FRAMEGEN,
|
||||
};
|
||||
|
||||
struct dpu_fetchunit;
|
||||
|
||||
struct dpu_fetchunit_ops {
|
||||
|
|
@ -554,6 +559,36 @@ void layerblend_position(struct dpu_layerblend *lb, int x, int y);
|
|||
struct dpu_layerblend *dpu_lb_get(struct dpu_soc *dpu, int id);
|
||||
void dpu_lb_put(struct dpu_layerblend *lb);
|
||||
|
||||
/* Signature Unit */
|
||||
#define MAX_DPU_SIGNATURE_WIN_NUM 8
|
||||
struct dpu_signature;
|
||||
void signature_shden(struct dpu_signature *sig, bool enable);
|
||||
void signature_shdldsel_local(struct dpu_signature *sig);
|
||||
void signature_shdldsel_global(struct dpu_signature *sig);
|
||||
void
|
||||
signature_global_panic(struct dpu_signature *sig, unsigned int win, bool enable);
|
||||
void
|
||||
signature_local_panic(struct dpu_signature *sig, unsigned int win, bool enable);
|
||||
void
|
||||
signature_alpha_mask(struct dpu_signature *sig, unsigned int win, bool enable);
|
||||
void signature_crc(struct dpu_signature *sig, unsigned int win, bool enable);
|
||||
void
|
||||
signature_eval_win(struct dpu_signature *sig, unsigned int win, bool enable);
|
||||
void signature_win(struct dpu_signature *sig, unsigned int win,
|
||||
int xul, int yul, int xlr, int ylr);
|
||||
void signature_crc_value(struct dpu_signature *sig, unsigned int win,
|
||||
u32 *red, u32 *green, u32 *blue);
|
||||
void signature_shdldreq(struct dpu_signature *sig, u8 win_mask);
|
||||
void signature_continuous_mode(struct dpu_signature *sig, bool enable);
|
||||
void signature_kick(struct dpu_signature *sig);
|
||||
bool signature_is_idle(struct dpu_signature *sig);
|
||||
void signature_wait_for_idle(struct dpu_signature *sig);
|
||||
bool signature_is_valid(struct dpu_signature *sig);
|
||||
bool signature_is_error(struct dpu_signature *sig, u8 *err_win_mask);
|
||||
struct dpu_signature *dpu_sig_get(struct dpu_soc *dpu, int id);
|
||||
void dpu_sig_put(struct dpu_signature *sig);
|
||||
struct dpu_signature *dpu_aux_sig_peek(struct dpu_signature *sig);
|
||||
|
||||
/* Store Unit */
|
||||
struct dpu_store;
|
||||
void store_pixengcfg_syncmode_fixup(struct dpu_store *st, bool enable);
|
||||
|
|
|
|||
Loading…
Reference in New Issue