Pin control fixes for the v4.10 series.
Driver fixes only: - One fix to the Berlin driver making the SD card work fully again. - One fix to the Allwinner/sunxi bias function: one premature change needs to be partially reverted. - The remaining four patches are to Intel embedded SoCs: baytrail (three patches) and merrifield (one patch): register access debounce fixes and a missing spinlock. -----BEGIN PGP SIGNATURE----- iQIcBAABAgAGBQJYkaCaAAoJEEEQszewGV1zcFIQALbJdTw3NP4PhFCdOFH3PJLq JoFGNf5plpcQOV8GcMZvallUPmckdE99aO1VZkpDlJJSbrx3SrqhbxcVdL98Hj8+ MrMHXwb/tB5i35Ykn8P/2uh40qKCfTNyJg5KC3xW/jPBt2/yMj3jpCUuhsQYFC66 1gDiM+nwrWD/8+TQ4C0d34+Of2FLSOddH9oyH7xA7A54/w53glfg09Zx49pJSg+d IRtvFVKYTSSS3gQlRkmXxV+gyjQA1oKgpR7EAM5USBYMObdPMona6/I93wcgT/8s tPlg+wtspIkTShZ1KtbWghz4Gjsc4tYNxwsUkJ2tiqUYHHt9j+Z4UYxyYGBJMZPh 9YLcZJWErMvnxYoQXGE31UlPYaq7+al9D1woX7RlRnGQavATFxJZ2Smt+CqqXoUE WcJcWGNMA1jpF5rmpnz+7a65W2fXtGJg2KRwCsk1XEi/5qISndSAscXocX7AZtjv mk5X/d6F2fwzeRJkjeCIdZ62NjlDJtlrbK3LqWh72rlyId7tycGKDwzv7gAWwI6B AQIy5n8iakjGL8eTYGiPlz/HlORRAAxw5Qg0NMT9Q6Npqg9aozwuptJGOTA6Gb+Z azU0c7bca59/bmNrH8iAuFPgz/TWu6wQH3Qvlr8xWXJ4xTz2Ol8br5QBKp3xdck1 ++CT6tcdmi6c4poX8W3K =Smhk -----END PGP SIGNATURE----- Merge tag 'pinctrl-v4.10-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl Pull pin control fixes from Linus Walleij: "Another week, another set of pin control fixes. The subsystem has seen high patch-spot activity recently. The majority of the patches are for Intel, I vaguely think it mostly concern phones, tablets and maybe chromebooks and even laptops with this Intel Atom family chips. Driver fixes only: - one fix to the Berlin driver making the SD card work fully again. - one fix to the Allwinner/sunxi bias function: one premature change needs to be partially reverted. - the remaining four patches are to Intel embedded SoCs: baytrail (three patches) and merrifield (one patch): register access debounce fixes and a missing spinlock" * tag 'pinctrl-v4.10-4' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: baytrail: Add missing spinlock usage in byt_gpio_irq_handler pinctrl: baytrail: Debounce register is one per community pinctrl: baytrail: Rectify debounce support (part 2) pinctrl: intel: merrifield: Add missed check in mrfld_config_set() pinctrl: sunxi: Don't enforce bias disable (for now) pinctrl: berlin-bg4ct: fix the value for "sd1a" of pin SCRD0_CRD_PRES
This commit is contained in:
commit
c325b35337
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@ -217,7 +217,7 @@ static const struct berlin_desc_group berlin4ct_soc_pinctrl_groups[] = {
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BERLIN_PINCTRL_GROUP("SCRD0_CRD_PRES", 0xc, 0x3, 0x15,
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BERLIN_PINCTRL_FUNCTION(0x0, "gpio"), /* GPIO20 */
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BERLIN_PINCTRL_FUNCTION(0x1, "scrd0"), /* crd pres */
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BERLIN_PINCTRL_FUNCTION(0x1, "sd1a")), /* DAT3 */
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BERLIN_PINCTRL_FUNCTION(0x3, "sd1a")), /* DAT3 */
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BERLIN_PINCTRL_GROUP("SPI1_SS0n", 0xc, 0x3, 0x18,
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BERLIN_PINCTRL_FUNCTION(0x0, "spi1"), /* SS0n */
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BERLIN_PINCTRL_FUNCTION(0x1, "gpio"), /* GPIO37 */
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@ -731,16 +731,23 @@ static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
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int reg)
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{
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struct byt_community *comm = byt_get_community(vg, offset);
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u32 reg_offset = 0;
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u32 reg_offset;
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if (!comm)
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return NULL;
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offset -= comm->pin_base;
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if (reg == BYT_INT_STAT_REG)
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switch (reg) {
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case BYT_INT_STAT_REG:
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reg_offset = (offset / 32) * 4;
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else
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break;
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case BYT_DEBOUNCE_REG:
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reg_offset = 0;
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break;
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default:
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reg_offset = comm->pad_map[offset] * 16;
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break;
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}
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return comm->reg_base + reg_offset + reg;
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}
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@ -1243,10 +1250,12 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
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debounce = readl(db_reg);
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debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
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if (arg)
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conf |= BYT_DEBOUNCE_EN;
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else
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conf &= ~BYT_DEBOUNCE_EN;
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switch (arg) {
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case 0:
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conf &= BYT_DEBOUNCE_EN;
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break;
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case 375:
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debounce |= BYT_DEBOUNCE_PULSE_375US;
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break;
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@ -1269,7 +1278,9 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
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debounce |= BYT_DEBOUNCE_PULSE_24MS;
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break;
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default:
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ret = -EINVAL;
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if (arg)
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ret = -EINVAL;
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break;
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}
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if (!ret)
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@ -1612,7 +1623,9 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
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continue;
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}
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raw_spin_lock(&vg->lock);
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pending = readl(reg);
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raw_spin_unlock(&vg->lock);
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for_each_set_bit(pin, &pending, 32) {
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virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
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generic_handle_irq(virq);
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@ -794,6 +794,9 @@ static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
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unsigned int i;
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int ret;
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if (!mrfld_buf_available(mp, pin))
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return -ENOTSUPP;
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for (i = 0; i < nconfigs; i++) {
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switch (pinconf_to_config_param(configs[i])) {
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case PIN_CONFIG_BIAS_DISABLE:
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@ -564,8 +564,7 @@ static int sunxi_pconf_group_set(struct pinctrl_dev *pctldev,
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val = arg / 10 - 1;
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break;
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case PIN_CONFIG_BIAS_DISABLE:
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val = 0;
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break;
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continue;
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case PIN_CONFIG_BIAS_PULL_UP:
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if (arg == 0)
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return -EINVAL;
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