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Renesas ARM Based SoC Soc Updates for v3.19

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* Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled
 * Add CA7 arch_timer initialization for r8a7794
 * Handle CA7 arch timer delay
 * Add shmobile_init_late() to sh7372
   - This is consistent with other shmobile SoCs
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Merge tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Pull "Renesas ARM Based SoC Soc Updates for v3.19" from Simon Horman:

* Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled
* Add CA7 arch_timer initialization for r8a7794
* Handle CA7 arch timer delay
* Add shmobile_init_late() to sh7372
  - This is consistent with other shmobile SoCs

* tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled
  ARM: shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794
  ARM: shmobile: sh7372: Add shmobile_init_late()
  ARM: shmobile: Handle CA7 arch timer delay

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2014-11-19 22:02:48 +01:00
parent 15fee17dba 3794705aeb
commit c39bacad19
4 changed files with 65 additions and 30 deletions
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1
arch/arm/mach-shmobile/Kconfig
View file

@ -1,5 +1,6 @@
config ARCH_SHMOBILE
bool
select ZONE_DMA if ARM_LPAE
config PM_RCAR
bool

70
arch/arm/mach-shmobile/setup-rcar-gen2.c
View file

@ -3,6 +3,7 @@
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Magnus Damm
* Copyright (C) 2014 Ulrich Hecht
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@ -24,6 +25,7 @@
#include <linux/dma-contiguous.h>
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/of.h>
#include <linux/of_fdt.h>
#include <asm/mach/arch.h>
#include "common.h"
@ -54,37 +56,61 @@ void __init rcar_gen2_timer_init(void)
{
#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
u32 mode = rcar_gen2_read_mode_pins();
bool is_e2 = (bool)of_find_compatible_node(NULL, NULL,
"renesas,r8a7794");
#endif
#ifdef CONFIG_ARM_ARCH_TIMER
void __iomem *base;
int extal_mhz = 0;
u32 freq;
/* At Linux boot time the r8a7790 arch timer comes up
* with the counter disabled. Moreover, it may also report
* a potentially incorrect fixed 13 MHz frequency. To be
* correct these registers need to be updated to use the
* frequency EXTAL / 2 which can be determined by the MD pins.
*/
if (is_e2) {
freq = 260000000 / 8; /* ZS / 8 */
/* CNTVOFF has to be initialized either from non-secure
* Hypervisor mode or secure Monitor mode with SCR.NS==1.
* If TrustZone is enabled then it should be handled by the
* secure code.
*/
asm volatile(
" cps 0x16\n"
" mrc p15, 0, r1, c1, c1, 0\n"
" orr r0, r1, #1\n"
" mcr p15, 0, r0, c1, c1, 0\n"
" isb\n"
" mov r0, #0\n"
" mcrr p15, 4, r0, r0, c14\n"
" isb\n"
" mcr p15, 0, r1, c1, c1, 0\n"
" isb\n"
" cps 0x13\n"
: : : "r0", "r1");
} else {
/* At Linux boot time the r8a7790 arch timer comes up
* with the counter disabled. Moreover, it may also report
* a potentially incorrect fixed 13 MHz frequency. To be
* correct these registers need to be updated to use the
* frequency EXTAL / 2 which can be determined by the MD pins.
*/
switch (mode & (MD(14) | MD(13))) {
case 0:
extal_mhz = 15;
break;
case MD(13):
extal_mhz = 20;
break;
case MD(14):
extal_mhz = 26;
break;
case MD(13) | MD(14):
extal_mhz = 30;
break;
switch (mode & (MD(14) | MD(13))) {
case 0:
extal_mhz = 15;
break;
case MD(13):
extal_mhz = 20;
break;
case MD(14):
extal_mhz = 26;
break;
case MD(13) | MD(14):
extal_mhz = 30;
break;
}
/* The arch timer frequency equals EXTAL / 2 */
freq = extal_mhz * (1000000 / 2);
}
/* The arch timer frequency equals EXTAL / 2 */
freq = extal_mhz * (1000000 / 2);
/* Remap "armgcnt address map" space */
base = ioremap(0xe6080000, PAGE_SIZE);

1
arch/arm/mach-shmobile/setup-sh7372.c
View file

@ -1012,6 +1012,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
.init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc,
.init_machine = sh7372_add_standard_devices_dt,
.init_late = shmobile_init_late,
.dt_compat = sh7372_boards_compat_dt,
MACHINE_END

23
arch/arm/mach-shmobile/timer.c
View file

@ -45,6 +45,7 @@ void __init shmobile_init_delay(void)
struct device_node *np, *cpus;
bool is_a7_a8_a9 = false;
bool is_a15 = false;
bool has_arch_timer = false;
u32 max_freq = 0;
cpus = of_find_node_by_path("/cpus");
@ -57,12 +58,16 @@ void __init shmobile_init_delay(void)
if (!of_property_read_u32(np, "clock-frequency", &freq))
max_freq = max(max_freq, freq);
if (of_device_is_compatible(np, "arm,cortex-a7") ||
of_device_is_compatible(np, "arm,cortex-a8") ||
of_device_is_compatible(np, "arm,cortex-a9"))
if (of_device_is_compatible(np, "arm,cortex-a8") ||
of_device_is_compatible(np, "arm,cortex-a9")) {
is_a7_a8_a9 = true;
else if (of_device_is_compatible(np, "arm,cortex-a15"))
} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
is_a7_a8_a9 = true;
has_arch_timer = true;
} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
is_a15 = true;
has_arch_timer = true;
}
}
of_node_put(cpus);
@ -70,10 +75,12 @@ void __init shmobile_init_delay(void)
if (!max_freq)
return;
if (is_a7_a8_a9)
shmobile_setup_delay_hz(max_freq, 1, 3);
else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
shmobile_setup_delay_hz(max_freq, 2, 4);
if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
if (is_a7_a8_a9)
shmobile_setup_delay_hz(max_freq, 1, 3);
else if (is_a15)
shmobile_setup_delay_hz(max_freq, 2, 4);
}
}
static void __init shmobile_late_time_init(void)