Renesas ARM Based SoC Soc Updates for v3.19
* Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled * Add CA7 arch_timer initialization for r8a7794 * Handle CA7 arch timer delay * Add shmobile_init_late() to sh7372 - This is consistent with other shmobile SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUWBX0AAoJENfPZGlqN0++oZoP/1BV0Lzhol3eQ/RlqG9maNCO iR2tAdfeScxwqD+VE8pHJQIoyYF8sfKKEaJxsyPl2KP1BzzBXGkNnsp35vNPG8p7 32AY27+98R7AqJ2ajKAqqdc7ooZLam1BW7kv99XmSKx/9n4Y1RKXaXVweRmxh3d5 dBaKGVX8ixl7yDZ7prsQqECzh7XN1/rhPXP50nq0aZtR0CRgAPzHyGGooc7s3zIz 7enlXev2u178I0YH9kujBbB/pjWCxrygKsB7gWp+t/klb9R0MWmVoB8/ae5rFRbq E+ULTVJ2G0cnhCTncu7N65/N69rmrbCGaGLBzKqV4Ve3qXImr0L6AqGmAGPMlqJT V+C44tGCjTJ7rc2gwv3Y6EPi/BQmEGRAGUp6GLBC0wexQdP6GRa7HrxsiRPuXrF6 OTG42oGqslMNemF0yZjzJU/SDutLYqYHhbqzl8akGr+PpB58ybjplM0mAyae/pp6 JTDYqCvlowsXN3FWgSZOIZ8UFM58UElGt9DBGCyEypTUADAFqD0SiUU7QCRFGKaj VhfgQ/gzwmKG19C1DgLTZv+8fzR/lvwBBtjwlP0io4Rd52rUGtmxcvH/0KV8INXq GsI9mEb6B4ZUFhG0Dgkna1XM9227PIQr126K/PDPjQPNHxVoVMQUuo9DrFNmXMt7 XEhA8eE9kxnf73DQEPB7 =bG2T -----END PGP SIGNATURE----- Merge tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Renesas ARM Based SoC Soc Updates for v3.19" from Simon Horman: * Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled * Add CA7 arch_timer initialization for r8a7794 * Handle CA7 arch timer delay * Add shmobile_init_late() to sh7372 - This is consistent with other shmobile SoCs * tag 'renesas-soc-for-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Select CONFIG_ZONE_DMA when CONFIG_ARM_LPAE is enabled ARM: shmobile: rcar-gen2: Add CA7 arch_timer initialization for r8a7794 ARM: shmobile: sh7372: Add shmobile_init_late() ARM: shmobile: Handle CA7 arch timer delay Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
c39bacad19
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@ -1,5 +1,6 @@
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config ARCH_SHMOBILE
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bool
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select ZONE_DMA if ARM_LPAE
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config PM_RCAR
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bool
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@ -3,6 +3,7 @@
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Magnus Damm
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* Copyright (C) 2014 Ulrich Hecht
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -24,6 +25,7 @@
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#include <linux/dma-contiguous.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_fdt.h>
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#include <asm/mach/arch.h>
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#include "common.h"
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@ -54,37 +56,61 @@ void __init rcar_gen2_timer_init(void)
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{
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#if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
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u32 mode = rcar_gen2_read_mode_pins();
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bool is_e2 = (bool)of_find_compatible_node(NULL, NULL,
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"renesas,r8a7794");
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#endif
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#ifdef CONFIG_ARM_ARCH_TIMER
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void __iomem *base;
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int extal_mhz = 0;
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u32 freq;
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/* At Linux boot time the r8a7790 arch timer comes up
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* with the counter disabled. Moreover, it may also report
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* a potentially incorrect fixed 13 MHz frequency. To be
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* correct these registers need to be updated to use the
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* frequency EXTAL / 2 which can be determined by the MD pins.
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*/
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if (is_e2) {
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freq = 260000000 / 8; /* ZS / 8 */
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/* CNTVOFF has to be initialized either from non-secure
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* Hypervisor mode or secure Monitor mode with SCR.NS==1.
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* If TrustZone is enabled then it should be handled by the
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* secure code.
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*/
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asm volatile(
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" cps 0x16\n"
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" mrc p15, 0, r1, c1, c1, 0\n"
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" orr r0, r1, #1\n"
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" mcr p15, 0, r0, c1, c1, 0\n"
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" isb\n"
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" mov r0, #0\n"
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" mcrr p15, 4, r0, r0, c14\n"
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" isb\n"
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" mcr p15, 0, r1, c1, c1, 0\n"
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" isb\n"
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" cps 0x13\n"
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: : : "r0", "r1");
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} else {
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/* At Linux boot time the r8a7790 arch timer comes up
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* with the counter disabled. Moreover, it may also report
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* a potentially incorrect fixed 13 MHz frequency. To be
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* correct these registers need to be updated to use the
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* frequency EXTAL / 2 which can be determined by the MD pins.
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*/
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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extal_mhz = 15;
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break;
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case MD(13):
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extal_mhz = 20;
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break;
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case MD(14):
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extal_mhz = 26;
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break;
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case MD(13) | MD(14):
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extal_mhz = 30;
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break;
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switch (mode & (MD(14) | MD(13))) {
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case 0:
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extal_mhz = 15;
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break;
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case MD(13):
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extal_mhz = 20;
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break;
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case MD(14):
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extal_mhz = 26;
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break;
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case MD(13) | MD(14):
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extal_mhz = 30;
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break;
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}
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/* The arch timer frequency equals EXTAL / 2 */
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freq = extal_mhz * (1000000 / 2);
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}
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/* The arch timer frequency equals EXTAL / 2 */
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freq = extal_mhz * (1000000 / 2);
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/* Remap "armgcnt address map" space */
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base = ioremap(0xe6080000, PAGE_SIZE);
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@ -1012,6 +1012,7 @@ DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
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.init_irq = sh7372_init_irq,
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.handle_irq = shmobile_handle_irq_intc,
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.init_machine = sh7372_add_standard_devices_dt,
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.init_late = shmobile_init_late,
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.dt_compat = sh7372_boards_compat_dt,
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MACHINE_END
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@ -45,6 +45,7 @@ void __init shmobile_init_delay(void)
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struct device_node *np, *cpus;
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bool is_a7_a8_a9 = false;
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bool is_a15 = false;
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bool has_arch_timer = false;
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u32 max_freq = 0;
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cpus = of_find_node_by_path("/cpus");
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@ -57,12 +58,16 @@ void __init shmobile_init_delay(void)
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if (!of_property_read_u32(np, "clock-frequency", &freq))
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max_freq = max(max_freq, freq);
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if (of_device_is_compatible(np, "arm,cortex-a7") ||
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of_device_is_compatible(np, "arm,cortex-a8") ||
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of_device_is_compatible(np, "arm,cortex-a9"))
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if (of_device_is_compatible(np, "arm,cortex-a8") ||
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of_device_is_compatible(np, "arm,cortex-a9")) {
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is_a7_a8_a9 = true;
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else if (of_device_is_compatible(np, "arm,cortex-a15"))
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} else if (of_device_is_compatible(np, "arm,cortex-a7")) {
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is_a7_a8_a9 = true;
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has_arch_timer = true;
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} else if (of_device_is_compatible(np, "arm,cortex-a15")) {
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is_a15 = true;
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has_arch_timer = true;
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}
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}
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of_node_put(cpus);
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if (!max_freq)
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return;
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if (is_a7_a8_a9)
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shmobile_setup_delay_hz(max_freq, 1, 3);
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else if (is_a15 && !IS_ENABLED(CONFIG_ARM_ARCH_TIMER))
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shmobile_setup_delay_hz(max_freq, 2, 4);
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if (!has_arch_timer || !IS_ENABLED(CONFIG_ARM_ARCH_TIMER)) {
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if (is_a7_a8_a9)
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shmobile_setup_delay_hz(max_freq, 1, 3);
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else if (is_a15)
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shmobile_setup_delay_hz(max_freq, 2, 4);
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}
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}
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static void __init shmobile_late_time_init(void)
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