clk: rockchip: rk3036: fix the div offset for emac clock
Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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@ -344,12 +344,12 @@ static struct rockchip_clk_branch rk3036_clk_branches[] __initdata = {
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RK2928_CLKGATE_CON(10), 5, GFLAGS),
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COMPOSITE_NOGATE(0, "mac_pll_src", mux_pll_src_3plls_p, 0,
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RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 4, 5, DFLAGS),
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RK2928_CLKSEL_CON(21), 0, 2, MFLAGS, 9, 5, DFLAGS),
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MUX(SCLK_MACREF, "mac_clk_ref", mux_mac_p, CLK_SET_RATE_PARENT,
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RK2928_CLKSEL_CON(21), 3, 1, MFLAGS),
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COMPOSITE_NOMUX(SCLK_MAC, "mac_clk", "mac_clk_ref", 0,
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RK2928_CLKSEL_CON(21), 9, 5, DFLAGS,
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RK2928_CLKSEL_CON(21), 4, 5, DFLAGS,
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RK2928_CLKGATE_CON(2), 6, GFLAGS),
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MUX(SCLK_HDMI, "dclk_hdmi", mux_dclk_p, 0,
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