KVM: inline kvm_apic_present() and kvm_lapic_enabled()
Those functions are used during interrupt injection. When inlined they become nops on the fast path. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>hifive-unleashed-5.1
Gleb Natapov
Avi Kivity
parent
54e9818f39
commit
c48f14966c
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@ -73,11 +73,6 @@
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static unsigned int min_timer_period_us = 500;
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module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
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static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
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{
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return *((u32 *) (apic->regs + reg_off));
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}
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static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
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{
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*((u32 *) (apic->regs + reg_off)) = val;
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@ -119,19 +114,11 @@ static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
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}
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struct static_key_deferred apic_hw_disabled __read_mostly;
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static inline int apic_hw_enabled(struct kvm_lapic *apic)
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{
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if (static_key_false(&apic_hw_disabled.key))
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return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
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return MSR_IA32_APICBASE_ENABLE;
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}
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struct static_key_deferred apic_sw_disabled __read_mostly;
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static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
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{
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if ((apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
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if ((kvm_apic_get_reg(apic, APIC_SPIV) ^ val) & APIC_SPIV_APIC_ENABLED) {
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if (val & APIC_SPIV_APIC_ENABLED)
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static_key_slow_dec_deferred(&apic_sw_disabled);
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else
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@ -140,23 +127,9 @@ static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
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apic_set_reg(apic, APIC_SPIV, val);
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}
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static inline int apic_sw_enabled(struct kvm_lapic *apic)
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{
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if (static_key_false(&apic_sw_disabled.key))
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return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
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return APIC_SPIV_APIC_ENABLED;
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}
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static inline int apic_enabled(struct kvm_lapic *apic)
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{
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return apic_sw_enabled(apic) && apic_hw_enabled(apic);
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}
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static inline bool vcpu_has_lapic(struct kvm_vcpu *vcpu)
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{
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if (static_key_false(&kvm_no_apic_vcpu))
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return vcpu->arch.apic;
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return true;
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return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
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}
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#define LVT_MASK \
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@ -168,34 +141,34 @@ static inline bool vcpu_has_lapic(struct kvm_vcpu *vcpu)
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static inline int kvm_apic_id(struct kvm_lapic *apic)
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{
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return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
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return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
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}
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static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
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{
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return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
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return !(kvm_apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
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}
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static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
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{
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return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
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return kvm_apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
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}
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static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
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{
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return ((apic_get_reg(apic, APIC_LVTT) &
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return ((kvm_apic_get_reg(apic, APIC_LVTT) &
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apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
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}
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static inline int apic_lvtt_period(struct kvm_lapic *apic)
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{
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return ((apic_get_reg(apic, APIC_LVTT) &
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return ((kvm_apic_get_reg(apic, APIC_LVTT) &
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apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
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}
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static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
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{
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return ((apic_get_reg(apic, APIC_LVTT) &
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return ((kvm_apic_get_reg(apic, APIC_LVTT) &
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apic->lapic_timer.timer_mode_mask) ==
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APIC_LVT_TIMER_TSCDEADLINE);
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}
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@ -211,7 +184,7 @@ void kvm_apic_set_version(struct kvm_vcpu *vcpu)
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struct kvm_cpuid_entry2 *feat;
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u32 v = APIC_VERSION;
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if (!vcpu_has_lapic(vcpu))
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if (!kvm_vcpu_has_lapic(vcpu))
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return;
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feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
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@ -319,7 +292,7 @@ int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
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* will cause vmexit immediately and the value will be recalculated
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* on the next vmentry.
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*/
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if (!vcpu_has_lapic(vcpu))
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if (!kvm_vcpu_has_lapic(vcpu))
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return 0;
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highest_irr = apic_find_highest_irr(vcpu->arch.apic);
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@ -404,8 +377,8 @@ static void apic_update_ppr(struct kvm_lapic *apic)
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u32 tpr, isrv, ppr, old_ppr;
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int isr;
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old_ppr = apic_get_reg(apic, APIC_PROCPRI);
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tpr = apic_get_reg(apic, APIC_TASKPRI);
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old_ppr = kvm_apic_get_reg(apic, APIC_PROCPRI);
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tpr = kvm_apic_get_reg(apic, APIC_TASKPRI);
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isr = apic_find_highest_isr(apic);
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isrv = (isr != -1) ? isr : 0;
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@ -441,13 +414,13 @@ int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
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u32 logical_id;
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if (apic_x2apic_mode(apic)) {
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logical_id = apic_get_reg(apic, APIC_LDR);
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logical_id = kvm_apic_get_reg(apic, APIC_LDR);
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return logical_id & mda;
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}
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logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
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logical_id = GET_APIC_LOGICAL_ID(kvm_apic_get_reg(apic, APIC_LDR));
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switch (apic_get_reg(apic, APIC_DFR)) {
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switch (kvm_apic_get_reg(apic, APIC_DFR)) {
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case APIC_DFR_FLAT:
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if (logical_id & mda)
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result = 1;
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@ -459,7 +432,7 @@ int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
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break;
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default:
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apic_debug("Bad DFR vcpu %d: %08x\n",
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apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
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apic->vcpu->vcpu_id, kvm_apic_get_reg(apic, APIC_DFR));
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break;
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}
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@ -617,7 +590,7 @@ static int apic_set_eoi(struct kvm_lapic *apic)
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apic_clear_isr(vector, apic);
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apic_update_ppr(apic);
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if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
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if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI) &&
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kvm_ioapic_handles_vector(apic->vcpu->kvm, vector)) {
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int trigger_mode;
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if (apic_test_vector(vector, apic->regs + APIC_TMR))
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@ -632,8 +605,8 @@ static int apic_set_eoi(struct kvm_lapic *apic)
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static void apic_send_ipi(struct kvm_lapic *apic)
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{
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u32 icr_low = apic_get_reg(apic, APIC_ICR);
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u32 icr_high = apic_get_reg(apic, APIC_ICR2);
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u32 icr_low = kvm_apic_get_reg(apic, APIC_ICR);
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u32 icr_high = kvm_apic_get_reg(apic, APIC_ICR2);
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struct kvm_lapic_irq irq;
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irq.vector = icr_low & APIC_VECTOR_MASK;
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@ -668,7 +641,7 @@ static u32 apic_get_tmcct(struct kvm_lapic *apic)
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ASSERT(apic != NULL);
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/* if initial count is 0, current count should also be 0 */
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if (apic_get_reg(apic, APIC_TMICT) == 0)
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if (kvm_apic_get_reg(apic, APIC_TMICT) == 0)
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return 0;
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remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
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@ -724,13 +697,13 @@ static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
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break;
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case APIC_PROCPRI:
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apic_update_ppr(apic);
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val = apic_get_reg(apic, offset);
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val = kvm_apic_get_reg(apic, offset);
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break;
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case APIC_TASKPRI:
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report_tpr_access(apic, false);
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/* fall thru */
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default:
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val = apic_get_reg(apic, offset);
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val = kvm_apic_get_reg(apic, offset);
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break;
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}
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@ -782,7 +755,7 @@ static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
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static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
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{
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return apic_hw_enabled(apic) &&
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return kvm_apic_hw_enabled(apic) &&
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addr >= apic->base_address &&
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addr < apic->base_address + LAPIC_MMIO_LENGTH;
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}
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@ -805,7 +778,7 @@ static void update_divide_count(struct kvm_lapic *apic)
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{
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u32 tmp1, tmp2, tdcr;
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tdcr = apic_get_reg(apic, APIC_TDCR);
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tdcr = kvm_apic_get_reg(apic, APIC_TDCR);
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tmp1 = tdcr & 0xf;
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tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
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apic->divide_count = 0x1 << (tmp2 & 0x7);
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@ -822,7 +795,7 @@ static void start_apic_timer(struct kvm_lapic *apic)
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if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
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/* lapic timer in oneshot or periodic mode */
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now = apic->lapic_timer.timer.base->get_time();
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apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
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apic->lapic_timer.period = (u64)kvm_apic_get_reg(apic, APIC_TMICT)
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* APIC_BUS_CYCLE_NS * apic->divide_count;
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if (!apic->lapic_timer.period)
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@ -854,7 +827,7 @@ static void start_apic_timer(struct kvm_lapic *apic)
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"timer initial count 0x%x, period %lldns, "
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"expire @ 0x%016" PRIx64 ".\n", __func__,
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APIC_BUS_CYCLE_NS, ktime_to_ns(now),
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apic_get_reg(apic, APIC_TMICT),
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kvm_apic_get_reg(apic, APIC_TMICT),
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apic->lapic_timer.period,
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ktime_to_ns(ktime_add_ns(now,
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apic->lapic_timer.period)));
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@ -886,7 +859,7 @@ static void start_apic_timer(struct kvm_lapic *apic)
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static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
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{
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int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
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int nmi_wd_enabled = apic_lvt_nmi_mode(kvm_apic_get_reg(apic, APIC_LVT0));
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if (apic_lvt_nmi_mode(lvt0_val)) {
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if (!nmi_wd_enabled) {
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@ -937,7 +910,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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case APIC_SPIV: {
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u32 mask = 0x3ff;
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if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
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if (kvm_apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
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mask |= APIC_SPIV_DIRECTED_EOI;
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apic_set_spiv(apic, val & mask);
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if (!(val & APIC_SPIV_APIC_ENABLED)) {
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@ -945,7 +918,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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u32 lvt_val;
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for (i = 0; i < APIC_LVT_NUM; i++) {
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lvt_val = apic_get_reg(apic,
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lvt_val = kvm_apic_get_reg(apic,
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APIC_LVTT + 0x10 * i);
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apic_set_reg(apic, APIC_LVTT + 0x10 * i,
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lvt_val | APIC_LVT_MASKED);
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@ -974,7 +947,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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case APIC_LVT1:
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case APIC_LVTERR:
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/* TODO: Check vector */
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if (!apic_sw_enabled(apic))
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if (!kvm_apic_sw_enabled(apic))
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val |= APIC_LVT_MASKED;
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val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
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@ -983,12 +956,12 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
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break;
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case APIC_LVTT:
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if ((apic_get_reg(apic, APIC_LVTT) &
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if ((kvm_apic_get_reg(apic, APIC_LVTT) &
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apic->lapic_timer.timer_mode_mask) !=
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(val & apic->lapic_timer.timer_mode_mask))
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hrtimer_cancel(&apic->lapic_timer.timer);
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if (!apic_sw_enabled(apic))
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if (!kvm_apic_sw_enabled(apic))
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val |= APIC_LVT_MASKED;
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val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
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apic_set_reg(apic, APIC_LVTT, val);
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@ -1067,7 +1040,7 @@ static int apic_mmio_write(struct kvm_io_device *this,
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void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
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{
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if (vcpu_has_lapic(vcpu))
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if (kvm_vcpu_has_lapic(vcpu))
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apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
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}
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EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
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@ -1084,7 +1057,7 @@ void kvm_free_lapic(struct kvm_vcpu *vcpu)
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if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
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static_key_slow_dec_deferred(&apic_hw_disabled);
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if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
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if (!(kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED))
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static_key_slow_dec_deferred(&apic_sw_disabled);
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if (apic->regs)
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@ -1103,7 +1076,7 @@ u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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if (!vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
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if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
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apic_lvtt_period(apic))
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return 0;
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@ -1114,7 +1087,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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if (!vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
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if (!kvm_vcpu_has_lapic(vcpu) || apic_lvtt_oneshot(apic) ||
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apic_lvtt_period(apic))
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return;
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@ -1127,21 +1100,21 @@ void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
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{
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struct kvm_lapic *apic = vcpu->arch.apic;
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if (!vcpu_has_lapic(vcpu))
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if (!kvm_vcpu_has_lapic(vcpu))
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return;
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apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
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| (apic_get_reg(apic, APIC_TASKPRI) & 4));
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| (kvm_apic_get_reg(apic, APIC_TASKPRI) & 4));
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}
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u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
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{
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u64 tpr;
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if (!vcpu_has_lapic(vcpu))
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if (!kvm_vcpu_has_lapic(vcpu))
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return 0;
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tpr = (u64) apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
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tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
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||||
|
||||
return (tpr & 0xf0) >> 4;
|
||||
}
|
||||
|
|
@ -1238,16 +1211,6 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
|
|||
vcpu->arch.apic_base, apic->base_address);
|
||||
}
|
||||
|
||||
bool kvm_apic_present(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return vcpu_has_lapic(vcpu) && apic_hw_enabled(vcpu->arch.apic);
|
||||
}
|
||||
|
||||
int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
|
||||
}
|
||||
|
||||
/*
|
||||
*----------------------------------------------------------------------
|
||||
* timer interface
|
||||
|
|
@ -1263,7 +1226,7 @@ int apic_has_pending_timer(struct kvm_vcpu *vcpu)
|
|||
{
|
||||
struct kvm_lapic *apic = vcpu->arch.apic;
|
||||
|
||||
if (vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
|
||||
if (kvm_vcpu_has_lapic(vcpu) && apic_enabled(apic) &&
|
||||
apic_lvt_enabled(apic, APIC_LVTT))
|
||||
return atomic_read(&apic->lapic_timer.pending);
|
||||
|
||||
|
|
@ -1272,10 +1235,10 @@ int apic_has_pending_timer(struct kvm_vcpu *vcpu)
|
|||
|
||||
int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
|
||||
{
|
||||
u32 reg = apic_get_reg(apic, lvt_type);
|
||||
u32 reg = kvm_apic_get_reg(apic, lvt_type);
|
||||
int vector, mode, trig_mode;
|
||||
|
||||
if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
|
||||
if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
|
||||
vector = reg & APIC_VECTOR_MASK;
|
||||
mode = reg & APIC_MODE_MASK;
|
||||
trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
|
||||
|
|
@ -1375,23 +1338,23 @@ int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
|
|||
struct kvm_lapic *apic = vcpu->arch.apic;
|
||||
int highest_irr;
|
||||
|
||||
if (!vcpu_has_lapic(vcpu) || !apic_enabled(apic))
|
||||
if (!kvm_vcpu_has_lapic(vcpu) || !apic_enabled(apic))
|
||||
return -1;
|
||||
|
||||
apic_update_ppr(apic);
|
||||
highest_irr = apic_find_highest_irr(apic);
|
||||
if ((highest_irr == -1) ||
|
||||
((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
|
||||
((highest_irr & 0xF0) <= kvm_apic_get_reg(apic, APIC_PROCPRI)))
|
||||
return -1;
|
||||
return highest_irr;
|
||||
}
|
||||
|
||||
int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
|
||||
u32 lvt0 = kvm_apic_get_reg(vcpu->arch.apic, APIC_LVT0);
|
||||
int r = 0;
|
||||
|
||||
if (!apic_hw_enabled(vcpu->arch.apic))
|
||||
if (!kvm_apic_hw_enabled(vcpu->arch.apic))
|
||||
r = 1;
|
||||
if ((lvt0 & APIC_LVT_MASKED) == 0 &&
|
||||
GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
|
||||
|
|
@ -1403,7 +1366,7 @@ void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
|
|||
{
|
||||
struct kvm_lapic *apic = vcpu->arch.apic;
|
||||
|
||||
if (!vcpu_has_lapic(vcpu))
|
||||
if (!kvm_vcpu_has_lapic(vcpu))
|
||||
return;
|
||||
|
||||
if (atomic_read(&apic->lapic_timer.pending) > 0) {
|
||||
|
|
@ -1432,7 +1395,7 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
|
|||
|
||||
kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
|
||||
kvm_apic_set_version(vcpu);
|
||||
apic_set_spiv(apic, apic_get_reg(apic, APIC_SPIV));
|
||||
apic_set_spiv(apic, kvm_apic_get_reg(apic, APIC_SPIV));
|
||||
|
||||
apic_update_ppr(apic);
|
||||
hrtimer_cancel(&apic->lapic_timer.timer);
|
||||
|
|
@ -1448,7 +1411,7 @@ void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
|
|||
{
|
||||
struct hrtimer *timer;
|
||||
|
||||
if (!vcpu_has_lapic(vcpu))
|
||||
if (!kvm_vcpu_has_lapic(vcpu))
|
||||
return;
|
||||
|
||||
timer = &vcpu->arch.apic->lapic_timer.timer;
|
||||
|
|
@ -1549,7 +1512,7 @@ void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
|
|||
if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
|
||||
return;
|
||||
|
||||
tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
|
||||
tpr = kvm_apic_get_reg(apic, APIC_TASKPRI) & 0xff;
|
||||
max_irr = apic_find_highest_irr(apic);
|
||||
if (max_irr < 0)
|
||||
max_irr = 0;
|
||||
|
|
@ -1608,7 +1571,7 @@ int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
|
|||
{
|
||||
struct kvm_lapic *apic = vcpu->arch.apic;
|
||||
|
||||
if (!vcpu_has_lapic(vcpu))
|
||||
if (!kvm_vcpu_has_lapic(vcpu))
|
||||
return 1;
|
||||
|
||||
/* if this is ICR write vector before command */
|
||||
|
|
@ -1622,7 +1585,7 @@ int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
|
|||
struct kvm_lapic *apic = vcpu->arch.apic;
|
||||
u32 low, high = 0;
|
||||
|
||||
if (!vcpu_has_lapic(vcpu))
|
||||
if (!kvm_vcpu_has_lapic(vcpu))
|
||||
return 1;
|
||||
|
||||
if (apic_reg_read(apic, reg, 4, &low))
|
||||
|
|
|
|||
|
|
@ -55,8 +55,6 @@ int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
|
|||
u64 kvm_get_apic_base(struct kvm_vcpu *vcpu);
|
||||
void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data);
|
||||
void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu);
|
||||
int kvm_lapic_enabled(struct kvm_vcpu *vcpu);
|
||||
bool kvm_apic_present(struct kvm_vcpu *vcpu);
|
||||
int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu);
|
||||
|
||||
u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu);
|
||||
|
|
@ -79,4 +77,47 @@ static inline bool kvm_hv_vapic_assist_page_enabled(struct kvm_vcpu *vcpu)
|
|||
|
||||
int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data);
|
||||
void kvm_lapic_init(void);
|
||||
|
||||
static inline u32 kvm_apic_get_reg(struct kvm_lapic *apic, int reg_off)
|
||||
{
|
||||
return *((u32 *) (apic->regs + reg_off));
|
||||
}
|
||||
|
||||
extern struct static_key kvm_no_apic_vcpu;
|
||||
|
||||
static inline bool kvm_vcpu_has_lapic(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
if (static_key_false(&kvm_no_apic_vcpu))
|
||||
return vcpu->arch.apic;
|
||||
return true;
|
||||
}
|
||||
|
||||
extern struct static_key_deferred apic_hw_disabled;
|
||||
|
||||
static inline int kvm_apic_hw_enabled(struct kvm_lapic *apic)
|
||||
{
|
||||
if (static_key_false(&apic_hw_disabled.key))
|
||||
return apic->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
|
||||
return MSR_IA32_APICBASE_ENABLE;
|
||||
}
|
||||
|
||||
extern struct static_key_deferred apic_sw_disabled;
|
||||
|
||||
static inline int kvm_apic_sw_enabled(struct kvm_lapic *apic)
|
||||
{
|
||||
if (static_key_false(&apic_sw_disabled.key))
|
||||
return kvm_apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
|
||||
return APIC_SPIV_APIC_ENABLED;
|
||||
}
|
||||
|
||||
static inline bool kvm_apic_present(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return kvm_vcpu_has_lapic(vcpu) && kvm_apic_hw_enabled(vcpu->arch.apic);
|
||||
}
|
||||
|
||||
static inline int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
|
||||
{
|
||||
return kvm_apic_present(vcpu) && kvm_apic_sw_enabled(vcpu->arch.apic);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue