memory: samsung: exynos5422-dmc: Do not ignore return code of regmap_read()
Check for regmap_read() return code before using the read value in following write in exynos5_switch_timing_regs(). Pass reading error code to the callers. This does not introduce proper error handling for such failed reads (and obviously regmap_write() error is still ignored) because the driver ignored this in all places. Therefor it only fixes reported issue while matching current driver coding style: drivers/memory/samsung/exynos5422-dmc.c: In function 'exynos5_switch_timing_regs': >> drivers/memory/samsung/exynos5422-dmc.c:216:6: warning: variable 'ret' set but not used [-Wunused-but-set-variable] Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -270,12 +270,14 @@ static int find_target_freq_idx(struct exynos5_dmc *dmc,
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* This function switches between these banks according to the
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* This function switches between these banks according to the
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* currently used clock source.
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* currently used clock source.
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*/
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*/
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static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
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static int exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
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{
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{
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unsigned int reg;
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unsigned int reg;
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int ret;
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int ret;
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ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
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ret = regmap_read(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, ®);
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if (ret)
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return ret;
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if (set)
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if (set)
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reg |= EXYNOS5_TIMING_SET_SWI;
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reg |= EXYNOS5_TIMING_SET_SWI;
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@ -283,6 +285,8 @@ static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set)
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reg &= ~EXYNOS5_TIMING_SET_SWI;
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reg &= ~EXYNOS5_TIMING_SET_SWI;
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regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
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regmap_write(dmc->clk_regmap, CDREX_LPDDR3PHY_CON3, reg);
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return 0;
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}
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}
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/**
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/**
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@ -516,7 +520,7 @@ exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc,
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/*
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/*
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* Delays are long enough, so use them for the new coming clock.
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* Delays are long enough, so use them for the new coming clock.
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*/
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*/
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exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
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ret = exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS);
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return ret;
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return ret;
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}
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}
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@ -577,7 +581,9 @@ exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc,
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clk_set_rate(dmc->fout_bpll, target_rate);
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clk_set_rate(dmc->fout_bpll, target_rate);
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exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
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ret = exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS);
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if (ret)
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goto disable_clocks;
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ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
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ret = clk_set_parent(dmc->mout_mclk_cdrex, dmc->mout_bpll);
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if (ret)
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if (ret)
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