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Documentation: dtb: xgene: Add rxlos GPIO mapping

Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Iyappan Subramanian <isubramanian@apm.com>
Tested-by: Fushen Chen <fchen@apm.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
hifive-unleashed-5.1
Iyappan Subramanian 2016-08-12 22:05:46 -07:00 committed by David S. Miller
parent 72d256439f
commit c50fc2622c
1 changed files with 3 additions and 0 deletions

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@ -47,6 +47,9 @@ Optional properties:
Valid values are between 0 to 7, that maps to
273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
Default value is 2, which corresponds to 899 ps
- rxlos-gpios: Input gpio from SFP+ module to indicate availability of
incoming signal.
Example:
menetclk: menetclk {