spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses
This feature should not be enabled in release but can be useful for developers who need to monitor register accesses at some specific places. Helped me identify a bug in u-boot, by comparing the register accesses from the linux driver with the ones from its u-boot variant. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20200320065058.891221-1-tudor.ambarus@microchip.com Signed-off-by: Mark Brown <broonie@kernel.org>alistair/sensors
Tudor Ambarus
Mark Brown
parent
138f56ef91
commit
c528ecfbef
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@ -173,6 +173,81 @@ static const struct atmel_qspi_mode atmel_qspi_modes[] = {
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{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
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};
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#ifdef VERBOSE_DEBUG
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static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
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{
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switch (offset) {
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case QSPI_CR:
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return "CR";
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case QSPI_MR:
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return "MR";
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case QSPI_RD:
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return "MR";
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case QSPI_TD:
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return "TD";
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case QSPI_SR:
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return "SR";
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case QSPI_IER:
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return "IER";
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case QSPI_IDR:
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return "IDR";
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case QSPI_IMR:
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return "IMR";
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case QSPI_SCR:
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return "SCR";
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case QSPI_IAR:
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return "IAR";
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case QSPI_ICR:
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return "ICR/WICR";
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case QSPI_IFR:
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return "IFR";
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case QSPI_RICR:
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return "RICR";
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case QSPI_SMR:
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return "SMR";
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case QSPI_SKR:
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return "SKR";
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case QSPI_WPMR:
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return "WPMR";
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case QSPI_WPSR:
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return "WPSR";
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case QSPI_VERSION:
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return "VERSION";
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default:
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snprintf(tmp, sz, "0x%02x", offset);
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break;
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}
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return tmp;
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}
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#endif /* VERBOSE_DEBUG */
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static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
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{
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u32 value = readl_relaxed(aq->regs + offset);
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#ifdef VERBOSE_DEBUG
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char tmp[8];
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dev_vdbg(&aq->pdev->dev, "read 0x%08x from %s\n", value,
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atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
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#endif /* VERBOSE_DEBUG */
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return value;
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}
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static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
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{
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#ifdef VERBOSE_DEBUG
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char tmp[8];
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dev_vdbg(&aq->pdev->dev, "write 0x%08x into %s\n", value,
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atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
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#endif /* VERBOSE_DEBUG */
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writel_relaxed(value, aq->regs + offset);
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}
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static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
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const struct atmel_qspi_mode *mode)
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{
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@ -293,32 +368,32 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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/* Clear pending interrupts */
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(void)readl_relaxed(aq->regs + QSPI_SR);
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(void)atmel_qspi_read(aq, QSPI_SR);
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if (aq->caps->has_ricr) {
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if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
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ifr |= QSPI_IFR_APBTFRTYP_READ;
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/* Set QSPI Instruction Frame registers */
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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atmel_qspi_write(iar, aq, QSPI_IAR);
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if (op->data.dir == SPI_MEM_DATA_IN)
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writel_relaxed(icr, aq->regs + QSPI_RICR);
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atmel_qspi_write(icr, aq, QSPI_RICR);
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else
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writel_relaxed(icr, aq->regs + QSPI_WICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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atmel_qspi_write(icr, aq, QSPI_WICR);
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atmel_qspi_write(ifr, aq, QSPI_IFR);
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} else {
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if (op->data.dir == SPI_MEM_DATA_OUT)
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ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
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/* Set QSPI Instruction Frame registers */
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writel_relaxed(iar, aq->regs + QSPI_IAR);
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writel_relaxed(icr, aq->regs + QSPI_ICR);
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writel_relaxed(ifr, aq->regs + QSPI_IFR);
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atmel_qspi_write(iar, aq, QSPI_IAR);
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atmel_qspi_write(icr, aq, QSPI_ICR);
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atmel_qspi_write(ifr, aq, QSPI_IFR);
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}
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return 0;
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@ -345,7 +420,7 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)readl_relaxed(aq->regs + QSPI_IFR);
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(void)atmel_qspi_read(aq, QSPI_IFR);
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/* Send/Receive data */
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if (op->data.dir == SPI_MEM_DATA_IN)
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@ -356,22 +431,22 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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op->data.nbytes);
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/* Release the chip-select */
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writel_relaxed(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
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atmel_qspi_write(QSPI_CR_LASTXFER, aq, QSPI_CR);
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}
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/* Poll INSTRuction End status */
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sr = readl_relaxed(aq->regs + QSPI_SR);
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sr = atmel_qspi_read(aq, QSPI_SR);
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if ((sr & QSPI_SR_CMD_COMPLETED) == QSPI_SR_CMD_COMPLETED)
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return err;
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/* Wait for INSTRuction End interrupt */
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reinit_completion(&aq->cmd_completion);
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aq->pending = sr & QSPI_SR_CMD_COMPLETED;
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writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IER);
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atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IER);
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if (!wait_for_completion_timeout(&aq->cmd_completion,
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msecs_to_jiffies(1000)))
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err = -ETIMEDOUT;
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writel_relaxed(QSPI_SR_CMD_COMPLETED, aq->regs + QSPI_IDR);
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atmel_qspi_write(QSPI_SR_CMD_COMPLETED, aq, QSPI_IDR);
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return err;
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}
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@ -410,7 +485,7 @@ static int atmel_qspi_setup(struct spi_device *spi)
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scbr--;
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aq->scr = QSPI_SCR_SCBR(scbr);
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writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
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atmel_qspi_write(aq->scr, aq, QSPI_SCR);
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return 0;
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}
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@ -418,14 +493,14 @@ static int atmel_qspi_setup(struct spi_device *spi)
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static void atmel_qspi_init(struct atmel_qspi *aq)
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{
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/* Reset the QSPI controller */
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writel_relaxed(QSPI_CR_SWRST, aq->regs + QSPI_CR);
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atmel_qspi_write(QSPI_CR_SWRST, aq, QSPI_CR);
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/* Set the QSPI controller by default in Serial Memory Mode */
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writel_relaxed(QSPI_MR_SMM, aq->regs + QSPI_MR);
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atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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/* Enable the QSPI controller */
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writel_relaxed(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
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atmel_qspi_write(QSPI_CR_QSPIEN, aq, QSPI_CR);
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}
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static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
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@ -433,8 +508,8 @@ static irqreturn_t atmel_qspi_interrupt(int irq, void *dev_id)
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struct atmel_qspi *aq = dev_id;
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u32 status, mask, pending;
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status = readl_relaxed(aq->regs + QSPI_SR);
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mask = readl_relaxed(aq->regs + QSPI_IMR);
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status = atmel_qspi_read(aq, QSPI_SR);
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mask = atmel_qspi_read(aq, QSPI_IMR);
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pending = status & mask;
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if (!pending)
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@ -569,7 +644,7 @@ static int atmel_qspi_remove(struct platform_device *pdev)
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struct atmel_qspi *aq = spi_controller_get_devdata(ctrl);
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spi_unregister_controller(ctrl);
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writel_relaxed(QSPI_CR_QSPIDIS, aq->regs + QSPI_CR);
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atmel_qspi_write(QSPI_CR_QSPIDIS, aq, QSPI_CR);
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clk_disable_unprepare(aq->qspick);
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clk_disable_unprepare(aq->pclk);
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return 0;
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@ -596,7 +671,7 @@ static int __maybe_unused atmel_qspi_resume(struct device *dev)
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atmel_qspi_init(aq);
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writel_relaxed(aq->scr, aq->regs + QSPI_SCR);
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atmel_qspi_write(aq->scr, aq, QSPI_SCR);
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return 0;
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}
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