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perf vendor events intel: Update GoldmontPlus to v1.01 

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Link: https://lkml.kernel.org/r/20190315165219.GA21223@tassilo.jf.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
hifive-unleashed-5.2
Andi Kleen 2019-03-14 14:55:53 -07:00 committed by Arnaldo Carvalho de Melo
parent f3ef08583e
commit c53dd58988
3 changed files with 51 additions and 37 deletions
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42
tools/perf/pmu-events/arch/x86/goldmontplus/cache.json
View File

@ -92,7 +92,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Locked load uops retired (Precise event capable)"
"BriefDescription": "Locked load uops retired (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -104,7 +105,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that split a cache-line (Precise event capable)"
"BriefDescription": "Load uops retired that split a cache-line (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -116,7 +118,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"SampleAfterValue": "200003",
"BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)"
"BriefDescription": "Stores uops retired that split a cache-line (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -128,7 +131,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.SPLIT",
"SampleAfterValue": "200003",
"BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)"
"BriefDescription": "Memory uops retired that split a cache-line (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -140,7 +144,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired (Precise event capable)"
"BriefDescription": "Load uops retired (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -152,7 +157,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"SampleAfterValue": "200003",
"BriefDescription": "Store uops retired (Precise event capable)"
"BriefDescription": "Store uops retired (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -164,7 +170,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL",
"SampleAfterValue": "200003",
"BriefDescription": "Memory uops retired (Precise event capable)"
"BriefDescription": "Memory uops retired (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -176,7 +183,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)"
"BriefDescription": "Load uops retired that hit L1 data cache (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -188,7 +196,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that hit L2 (Precise event capable)"
"BriefDescription": "Load uops retired that hit L2 (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -200,7 +209,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)"
"BriefDescription": "Load uops retired that missed L1 data cache (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -212,7 +222,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that missed L2 (Precise event capable)"
"BriefDescription": "Load uops retired that missed L2 (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -224,7 +235,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.HITM",
"SampleAfterValue": "200003",
"BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)"
"BriefDescription": "Memory uop retired where cross core or cross module HITM occurred (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -236,7 +248,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Loads retired that hit WCB (Precise event capable)"
"BriefDescription": "Loads retired that hit WCB (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -248,7 +261,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
"SampleAfterValue": "200003",
"BriefDescription": "Loads retired that came from DRAM (Precise event capable)"
"BriefDescription": "Loads retired that came from DRAM (Precise event capable)",
"Data_LA": "1"
},
{
"CollectPEBSRecord": "1",

5
tools/perf/pmu-events/arch/x86/goldmontplus/pipeline.json
View File

@ -3,7 +3,6 @@
"PEBS": "2",
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of instructions that retire execution. For instructions that consist of multiple uops, this event counts the retirement of the last uop of the instruction. The counter continues counting during hardware interrupts, traps, and inside interrupt handlers. This event uses fixed counter 0. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 0",
"UMask": "0x1",
"PEBScounters": "32",
@ -15,7 +14,6 @@
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 1",
"UMask": "0x2",
"PEBScounters": "33",
@ -27,7 +25,6 @@
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. In mobile systems the core frequency may change from time. This event is not affected by core frequency changes but counts as if the core is running at the maximum frequency all the time. This event uses fixed counter 2. You cannot collect a PEBs record for this event.",
"EventCode": "0x00",
"Counter": "Fixed counter 2",
"UMask": "0x3",
"PEBScounters": "34",
@ -231,7 +228,7 @@
},
{
"CollectPEBSRecord": "1",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel architecture processors.",
"PublicDescription": "Counts the number of times that the processor detects that a program is writing to a code section and has to perform a machine clear because of that modification. Self-modifying code (SMC) causes a severe penalty in all Intel\u00ae architecture processors.",
"EventCode": "0xC3",
"Counter": "0,1,2,3",
"UMask": "0x1",

9
tools/perf/pmu-events/arch/x86/goldmontplus/virtual-memory.json
View File

@ -189,7 +189,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS",
"SampleAfterValue": "200003",
"BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)"
"BriefDescription": "Load uops retired that missed the DTLB (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -201,7 +202,8 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS_STORES",
"SampleAfterValue": "200003",
"BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)"
"BriefDescription": "Store uops retired that missed the DTLB (Precise event capable)",
"Data_LA": "1"
},
{
"PEBS": "2",
@ -213,6 +215,7 @@
"PEBScounters": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.DTLB_MISS",
"SampleAfterValue": "200003",
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)"
"BriefDescription": "Memory uops retired that missed the DTLB (Precise event capable)",
"Data_LA": "1"
}
]