mvsas: Add SGPIO support to Marvell 94xx
Add SGPIO support to Marvell 94xx. Signed-off-by: Wilfried Weissmann <Wilfried.Weissmann@gmx.at> Reviewed-by: James Bottomley <James.Bottomley@HansenPartnership.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>hifive-unleashed-5.1
Wilfried Weissmann
Martin K. Petersen
parent
5f985d88ba
commit
c56f5f1de3
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@ -330,6 +330,51 @@ static void mvs_94xx_phy_enable(struct mvs_info *mvi, u32 phy_id)
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mvs_write_port_vsr_data(mvi, phy_id, tmp & 0xfd7fffff);
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}
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static void mvs_94xx_sgpio_init(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs_ex - 0x10200;
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u32 tmp;
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tmp = mr32(MVS_HST_CHIP_CONFIG);
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tmp |= 0x100;
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mw32(MVS_HST_CHIP_CONFIG, tmp);
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mw32(MVS_SGPIO_CTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
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MVS_SGPIO_CTRL_SDOUT_AUTO << MVS_SGPIO_CTRL_SDOUT_SHIFT);
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mw32(MVS_SGPIO_CFG1 + MVS_SGPIO_HOST_OFFSET * mvi->id,
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8 << MVS_SGPIO_CFG1_LOWA_SHIFT |
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8 << MVS_SGPIO_CFG1_HIA_SHIFT |
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4 << MVS_SGPIO_CFG1_LOWB_SHIFT |
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4 << MVS_SGPIO_CFG1_HIB_SHIFT |
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2 << MVS_SGPIO_CFG1_MAXACTON_SHIFT |
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1 << MVS_SGPIO_CFG1_FORCEACTOFF_SHIFT
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);
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mw32(MVS_SGPIO_CFG2 + MVS_SGPIO_HOST_OFFSET * mvi->id,
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(300000 / 100) << MVS_SGPIO_CFG2_CLK_SHIFT | /* 100kHz clock */
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66 << MVS_SGPIO_CFG2_BLINK_SHIFT /* (66 * 0,121 Hz?)*/
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);
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mw32(MVS_SGPIO_CFG0 + MVS_SGPIO_HOST_OFFSET * mvi->id,
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MVS_SGPIO_CFG0_ENABLE |
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MVS_SGPIO_CFG0_BLINKA |
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MVS_SGPIO_CFG0_BLINKB |
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/* 3*4 data bits / PDU */
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(12 - 1) << MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT
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);
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mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
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DEFAULT_SGPIO_BITS);
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mw32(MVS_SGPIO_DSRC + MVS_SGPIO_HOST_OFFSET * mvi->id,
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((mvi->id * 4) + 3) << (8 * 3) |
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((mvi->id * 4) + 2) << (8 * 2) |
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((mvi->id * 4) + 1) << (8 * 1) |
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((mvi->id * 4) + 0) << (8 * 0));
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}
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static int mvs_94xx_init(struct mvs_info *mvi)
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{
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void __iomem *regs = mvi->regs;
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@ -533,6 +578,8 @@ static int mvs_94xx_init(struct mvs_info *mvi)
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/* Enable SRS interrupt */
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mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
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mvs_94xx_sgpio_init(mvi);
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return 0;
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}
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@ -1005,6 +1052,92 @@ static void mvs_94xx_tune_interrupt(struct mvs_info *mvi, u32 time)
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}
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static int mvs_94xx_gpio_write(struct mvs_prv_info *mvs_prv,
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u8 reg_type, u8 reg_index,
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u8 reg_count, u8 *write_data)
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{
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int i;
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switch (reg_type) {
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case SAS_GPIO_REG_TX_GP:
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if (reg_index == 0)
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return -EINVAL;
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if (reg_count > 1)
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return -EINVAL;
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if (reg_count == 0)
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return 0;
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/* maximum supported bits = hosts * 4 drives * 3 bits */
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for (i = 0; i < mvs_prv->n_host * 4 * 3; i++) {
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/* select host */
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struct mvs_info *mvi = mvs_prv->mvi[i/(4*3)];
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void __iomem *regs = mvi->regs_ex - 0x10200;
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int drive = (i/3) & (4-1); /* drive number on host */
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u32 block = mr32(MVS_SGPIO_DCTRL +
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MVS_SGPIO_HOST_OFFSET * mvi->id);
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/*
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* if bit is set then create a mask with the first
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* bit of the drive set in the mask ...
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*/
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u32 bit = (write_data[i/8] & (1 << (i&(8-1)))) ?
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1<<(24-drive*8) : 0;
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/*
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* ... and then shift it to the right position based
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* on the led type (activity/id/fail)
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*/
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switch (i%3) {
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case 0: /* activity */
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block &= ~((0x7 << MVS_SGPIO_DCTRL_ACT_SHIFT)
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<< (24-drive*8));
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/* hardwire activity bit to SOF */
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block |= LED_BLINKA_SOF << (
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MVS_SGPIO_DCTRL_ACT_SHIFT +
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(24-drive*8));
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break;
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case 1: /* id */
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block &= ~((0x3 << MVS_SGPIO_DCTRL_LOC_SHIFT)
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<< (24-drive*8));
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block |= bit << MVS_SGPIO_DCTRL_LOC_SHIFT;
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break;
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case 2: /* fail */
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block &= ~((0x7 << MVS_SGPIO_DCTRL_ERR_SHIFT)
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<< (24-drive*8));
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block |= bit << MVS_SGPIO_DCTRL_ERR_SHIFT;
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break;
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}
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mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
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block);
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}
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return reg_count;
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case SAS_GPIO_REG_TX:
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if (reg_index + reg_count > mvs_prv->n_host)
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return -EINVAL;
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for (i = 0; i < reg_count; i++) {
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struct mvs_info *mvi = mvs_prv->mvi[i+reg_index];
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void __iomem *regs = mvi->regs_ex - 0x10200;
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mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
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be32_to_cpu(((u32 *) write_data)[i]));
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}
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return reg_count;
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}
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return -ENOSYS;
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}
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const struct mvs_dispatch mvs_94xx_dispatch = {
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"mv94xx",
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mvs_94xx_init,
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@ -1057,5 +1190,6 @@ const struct mvs_dispatch mvs_94xx_dispatch = {
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mvs_94xx_fix_dma,
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mvs_94xx_tune_interrupt,
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mvs_94xx_non_spec_ncq_error,
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mvs_94xx_gpio_write,
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};
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@ -38,6 +38,10 @@ enum VANIR_REVISION_ID {
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VANIR_C2_REV = 0xC2,
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};
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enum host_registers {
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MVS_HST_CHIP_CONFIG = 0x10104, /* chip configuration */
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};
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enum hw_registers {
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MVS_GBL_CTL = 0x04, /* global control */
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MVS_GBL_INT_STAT = 0x00, /* global irq status */
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@ -239,6 +243,73 @@ struct mvs_prd {
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__le32 im_len;
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} __attribute__ ((packed));
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enum sgpio_registers {
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MVS_SGPIO_HOST_OFFSET = 0x100, /* offset between hosts */
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MVS_SGPIO_CFG0 = 0xc200,
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MVS_SGPIO_CFG0_ENABLE = (1 << 0), /* enable pins */
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MVS_SGPIO_CFG0_BLINKB = (1 << 1), /* blink generators */
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MVS_SGPIO_CFG0_BLINKA = (1 << 2),
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MVS_SGPIO_CFG0_INVSCLK = (1 << 3), /* invert signal? */
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MVS_SGPIO_CFG0_INVSLOAD = (1 << 4),
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MVS_SGPIO_CFG0_INVSDOUT = (1 << 5),
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MVS_SGPIO_CFG0_SLOAD_FALLEDGE = (1 << 6), /* rise/fall edge? */
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MVS_SGPIO_CFG0_SDOUT_FALLEDGE = (1 << 7),
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MVS_SGPIO_CFG0_SDIN_RISEEDGE = (1 << 8),
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MVS_SGPIO_CFG0_MAN_BITLEN_SHIFT = 18, /* bits/frame manual mode */
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MVS_SGPIO_CFG0_AUT_BITLEN_SHIFT = 24, /* bits/frame auto mode */
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MVS_SGPIO_CFG1 = 0xc204, /* blink timing register */
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MVS_SGPIO_CFG1_LOWA_SHIFT = 0, /* A off time */
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MVS_SGPIO_CFG1_HIA_SHIFT = 4, /* A on time */
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MVS_SGPIO_CFG1_LOWB_SHIFT = 8, /* B off time */
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MVS_SGPIO_CFG1_HIB_SHIFT = 12, /* B on time */
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MVS_SGPIO_CFG1_MAXACTON_SHIFT = 16, /* max activity on time */
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/* force activity off time */
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MVS_SGPIO_CFG1_FORCEACTOFF_SHIFT = 20,
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/* stretch activity on time */
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MVS_SGPIO_CFG1_STRCHACTON_SHIFT = 24,
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/* stretch activiity off time */
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MVS_SGPIO_CFG1_STRCHACTOFF_SHIFT = 28,
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MVS_SGPIO_CFG2 = 0xc208, /* clock speed register */
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MVS_SGPIO_CFG2_CLK_SHIFT = 0,
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MVS_SGPIO_CFG2_BLINK_SHIFT = 20,
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MVS_SGPIO_CTRL = 0xc20c, /* SDOUT/SDIN mode control */
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MVS_SGPIO_CTRL_SDOUT_AUTO = 2,
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MVS_SGPIO_CTRL_SDOUT_SHIFT = 2,
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MVS_SGPIO_DSRC = 0xc220, /* map ODn bits to drives */
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MVS_SGPIO_DCTRL = 0xc238,
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MVS_SGPIO_DCTRL_ERR_SHIFT = 0,
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MVS_SGPIO_DCTRL_LOC_SHIFT = 3,
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MVS_SGPIO_DCTRL_ACT_SHIFT = 5,
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};
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enum sgpio_led_status {
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LED_OFF = 0,
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LED_ON = 1,
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LED_BLINKA = 2,
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LED_BLINKA_INV = 3,
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LED_BLINKA_SOF = 4,
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LED_BLINKA_EOF = 5,
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LED_BLINKB = 6,
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LED_BLINKB_INV = 7,
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};
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#define DEFAULT_SGPIO_BITS ((LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 3) | \
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(LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 2) | \
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(LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 1) | \
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(LED_BLINKA_SOF << \
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MVS_SGPIO_DCTRL_ACT_SHIFT) << (8 * 0))
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/*
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* these registers are accessed through port vendor
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* specific address/data registers
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@ -84,6 +84,8 @@ static struct sas_domain_function_template mvs_transport_ops = {
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.lldd_port_formed = mvs_port_formed,
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.lldd_port_deformed = mvs_port_deformed,
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.lldd_write_gpio = mvs_gpio_write,
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};
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static void mvs_phy_init(struct mvs_info *mvi, int phy_id)
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@ -2105,3 +2105,16 @@ int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
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return 0;
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}
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int mvs_gpio_write(struct sas_ha_struct *sha, u8 reg_type, u8 reg_index,
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u8 reg_count, u8 *write_data)
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{
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struct mvs_prv_info *mvs_prv = sha->lldd_ha;
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struct mvs_info *mvi = mvs_prv->mvi[0];
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if (MVS_CHIP_DISP->gpio_write) {
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return MVS_CHIP_DISP->gpio_write(mvs_prv, reg_type,
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reg_index, reg_count, write_data);
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}
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return -ENOSYS;
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}
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@ -103,6 +103,7 @@ enum dev_reset {
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};
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struct mvs_info;
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struct mvs_prv_info;
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struct mvs_dispatch {
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char *name;
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@ -172,6 +173,8 @@ struct mvs_dispatch {
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int buf_len, int from, void *prd);
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void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
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void (*non_spec_ncq_error)(struct mvs_info *mvi);
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int (*gpio_write)(struct mvs_prv_info *mvs_prv, u8 reg_type,
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u8 reg_index, u8 reg_count, u8 *write_data);
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};
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@ -476,5 +479,7 @@ void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
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void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
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int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
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struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
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int mvs_gpio_write(struct sas_ha_struct *, u8 reg_type, u8 reg_index,
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u8 reg_count, u8 *write_data);
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#endif
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