ARM: mach-shmobile: r8a7779: Allow initialisation of GIC by DT
This allows the GIC interrupt controller of the r8a7779 SoC to be initialised using a flattened device tree blob. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> --- v3 * Fix copy-paste error and use unique reg values for each CPU v2 As suggested by Mark Rutland * Add reg and device_type to cpus * Remove #address-cells from gichifive-unleashed-5.1
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@ -0,0 +1,50 @@
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/*
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* Device Tree Source for Renesas r8a7740
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Simon Horman
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/include/ "skeleton.dtsi"
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/ {
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compatible = "renesas,r8a7779";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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};
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};
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gic: interrupt-controller@f0001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0xf0001000 0x1000>,
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<0xf0000100 0x100>;
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};
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};
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@ -59,6 +59,7 @@ extern void r8a7740_pinmux_init(void);
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extern void r8a7740_pm_init(void);
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extern void r8a7779_init_irq(void);
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extern void r8a7779_init_irq_dt(void);
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extern void r8a7779_map_io(void);
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extern void r8a7779_earlytimer_init(void);
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extern void r8a7779_add_early_devices(void);
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@ -24,6 +24,7 @@
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#include <linux/io.h>
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#include <linux/irqchip/arm-gic.h>
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#include <mach/common.h>
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#include <linux/irqchip.h>
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#include <mach/intc.h>
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#include <mach/r8a7779.h>
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#include <asm/mach-types.h>
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@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
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return 0; /* always allow wakeup */
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}
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void __init r8a7779_init_irq(void)
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static void __init r8a7779_init_irq_common(void)
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{
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void __iomem *gic_dist_base = IOMEM(0xf0001000);
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void __iomem *gic_cpu_base = IOMEM(0xf0000100);
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/* use GIC to handle interrupts */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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gic_arch_extn.irq_set_wake = r8a7779_set_wake;
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/* route all interrupts to ARM */
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@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void)
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__raw_writel(0xbffffffc, INT2SMSKCR3);
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__raw_writel(0x003fee3f, INT2SMSKCR4);
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}
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void __init r8a7779_init_irq(void)
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{
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void __iomem *gic_dist_base = IOMEM(0xf0001000);
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void __iomem *gic_cpu_base = IOMEM(0xf0000100);
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/* use GIC to handle interrupts */
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gic_init(0, 29, gic_dist_base, gic_cpu_base);
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r8a7779_init_irq_common();
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}
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#ifdef CONFIG_OF
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void __init r8a7779_init_irq_dt(void)
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{
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irqchip_init();
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r8a7779_init_irq_common();
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}
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#endif
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