ARM: socfpga: dts: Correct the parent clock for l3_sp_clk and dbg_clk
The l3_sp_clk's parent should be the l3_mp_clk. This will account for the extra divider that is present for the l3_mp_clk. The dbg_clk's parent should be the dbg_at_clk. This will account for the extra divider that is present for the dbg_at_clk. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>hifive-unleashed-5.1
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@ -318,7 +318,7 @@
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l3_sp_clk: l3_sp_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&mainclk>;
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clocks = <&l3_mp_clk>;
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div-reg = <0x64 2 2>;
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};
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@ -349,7 +349,7 @@
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dbg_clk: dbg_clk {
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#clock-cells = <0>;
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compatible = "altr,socfpga-gate-clk";
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clocks = <&dbg_base_clk>;
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clocks = <&dbg_at_clk>;
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div-reg = <0x68 2 2>;
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clk-gate = <0x60 5>;
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};
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