drm/omap: Implement workaround for DRA7 errata ID:i932
Description of DRA7 Errata i932: In rare circumstances DPLL_VIDEO1 and DPLL_VIDEO2 PLL's may not lock on the first attempt during DSS initialization. When this occurs, a subsequent attempt to relock the PLL will result in PLL successfully locking. This patch does the following as per the errata recommendation: - retries locking the PLL upto 20 times. - The time to wait for a PLL lock set to 1000 REFCLK cycles. We use usleep_range to wait for 1000 REFCLK cycles in the us range. This tight constraint is imposed as a lock later than 1000 REFCLK cycles may have high jitter. - Criteria for PLL lock is extended from check on just the PLL_LOCK bit to check on 6 PLL_STATUS bits. Silicon Versions Impacted: DRA71, DRA72, DRA74, DRA76 - All silicon revisions AM57x - All silicon revisions OMAP4/5 are not impacted by this errata Signed-off-by: Venkateswara Rao Mandela <venkat.mandela@ti.com> [tomi.valkeinen@ti.com: ported to v4.14] Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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@ -180,6 +180,9 @@ struct dss_pll_hw {
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/* DRA7 errata i886: use high N & M to avoid jitter */
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bool errata_i886;
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/* DRA7 errata i932: retry pll lock on failure */
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bool errata_i932;
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};
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struct dss_pll {
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@ -16,6 +16,7 @@
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#define DSS_SUBSYS_NAME "PLL"
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/kernel.h>
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@ -381,6 +382,22 @@ static int dss_wait_hsdiv_ack(struct dss_pll *pll, u32 hsdiv_ack_mask)
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return -ETIMEDOUT;
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}
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static bool pll_is_locked(u32 stat)
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{
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/*
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* Required value for each bitfield listed below
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*
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* PLL_STATUS[6] = 0 PLL_BYPASS
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* PLL_STATUS[5] = 0 PLL_HIGHJITTER
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*
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* PLL_STATUS[3] = 0 PLL_LOSSREF
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* PLL_STATUS[2] = 0 PLL_RECAL
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* PLL_STATUS[1] = 1 PLL_LOCK
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* PLL_STATUS[0] = 1 PLL_CTRL_RESET_DONE
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*/
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return ((stat & 0x6f) == 0x3);
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}
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int dss_pll_write_config_type_a(struct dss_pll *pll,
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const struct dss_pll_clock_info *cinfo)
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{
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@ -436,18 +453,54 @@ int dss_pll_write_config_type_a(struct dss_pll *pll,
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l = FLD_MOD(l, 0, 25, 25); /* M7_CLOCK_EN */
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writel_relaxed(l, base + PLL_CONFIGURATION2);
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writel_relaxed(1, base + PLL_GO); /* PLL_GO */
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if (hw->errata_i932) {
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int cnt = 0;
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u32 sleep_time;
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const u32 max_lock_retries = 20;
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if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
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DSSERR("DSS DPLL GO bit not going down.\n");
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r = -EIO;
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goto err;
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}
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/*
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* Calculate wait time for PLL LOCK
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* 1000 REFCLK cycles in us.
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*/
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sleep_time = DIV_ROUND_UP(1000*1000*1000, cinfo->fint);
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if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
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DSSERR("cannot lock DSS DPLL\n");
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r = -EIO;
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goto err;
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for (cnt = 0; cnt < max_lock_retries; cnt++) {
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writel_relaxed(1, base + PLL_GO); /* PLL_GO */
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/**
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* read the register back to ensure the write is
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* flushed
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*/
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readl_relaxed(base + PLL_GO);
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usleep_range(sleep_time, sleep_time + 5);
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l = readl_relaxed(base + PLL_STATUS);
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if (pll_is_locked(l) &&
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!(readl_relaxed(base + PLL_GO) & 0x1))
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break;
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}
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if (cnt == max_lock_retries) {
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DSSERR("cannot lock PLL\n");
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r = -EIO;
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goto err;
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}
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} else {
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writel_relaxed(1, base + PLL_GO); /* PLL_GO */
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if (wait_for_bit_change(base + PLL_GO, 0, 0) != 0) {
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DSSERR("DSS DPLL GO bit not going down.\n");
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r = -EIO;
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goto err;
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}
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if (wait_for_bit_change(base + PLL_STATUS, 1, 1) != 1) {
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DSSERR("cannot lock DSS DPLL\n");
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r = -EIO;
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goto err;
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}
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}
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l = readl_relaxed(base + PLL_CONFIGURATION2);
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@ -134,6 +134,7 @@ static const struct dss_pll_hw dss_dra7_video_pll_hw = {
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.has_refsel = true,
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.errata_i886 = true,
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.errata_i932 = true,
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};
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struct dss_pll *dss_video_pll_init(struct dss_device *dss,
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