ARM: KVM: abstract most MMU operations
Move low level MMU-related operations to kvm_mmu.h. This makes the MMU code reusable by the arm64 port. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>hifive-unleashed-5.1
Marc Zyngier
Christoffer Dall
parent
c088f8f008
commit
c62ee2b227
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@ -19,6 +19,9 @@
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#ifndef __ARM_KVM_MMU_H__
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#define __ARM_KVM_MMU_H__
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#include <asm/cacheflush.h>
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#include <asm/pgalloc.h>
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int create_hyp_mappings(void *from, void *to);
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int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
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void free_hyp_pmds(void);
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@ -36,6 +39,16 @@ phys_addr_t kvm_mmu_get_httbr(void);
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int kvm_mmu_init(void);
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void kvm_clear_hyp_idmap(void);
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static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
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{
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pte_val(*pte) = new_pte;
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/*
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* flush_pmd_entry just takes a void pointer and cleans the necessary
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* cache entries, so we can reuse the function for ptes.
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*/
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flush_pmd_entry(pte);
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}
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static inline bool kvm_is_write_fault(unsigned long hsr)
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{
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unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
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@ -47,4 +60,49 @@ static inline bool kvm_is_write_fault(unsigned long hsr)
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return true;
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}
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static inline void kvm_clean_pgd(pgd_t *pgd)
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{
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clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
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}
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static inline void kvm_clean_pmd_entry(pmd_t *pmd)
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{
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clean_pmd_entry(pmd);
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}
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static inline void kvm_clean_pte(pte_t *pte)
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{
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clean_pte_table(pte);
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}
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static inline void kvm_set_s2pte_writable(pte_t *pte)
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{
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pte_val(*pte) |= L_PTE_S2_RDWR;
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}
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struct kvm;
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static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
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{
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/*
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* If we are going to insert an instruction page and the icache is
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* either VIPT or PIPT, there is a potential problem where the host
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* (or another VM) may have used the same page as this guest, and we
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* read incorrect data from the icache. If we're using a PIPT cache,
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* we can invalidate just that page, but if we are using a VIPT cache
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* we need to invalidate the entire icache - damn shame - as written
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* in the ARM ARM (DDI 0406C.b - Page B3-1393).
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*
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* VIVT caches are tagged using both the ASID and the VMID and doesn't
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* need any kind of flushing (DDI 0406C.b - Page B3-1392).
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*/
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if (icache_is_pipt()) {
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unsigned long hva = gfn_to_hva(kvm, gfn);
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__cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
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} else if (!icache_is_vivt_asid_tagged()) {
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/* any kind of VIPT cache */
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__flush_icache_all();
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}
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}
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#endif /* __ARM_KVM_MMU_H__ */
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@ -28,8 +28,6 @@
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#include <asm/kvm_mmio.h>
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#include <asm/kvm_asm.h>
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#include <asm/kvm_emulate.h>
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#include <asm/mach/map.h>
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#include <trace/events/kvm.h>
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#include "trace.h"
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@ -42,16 +40,6 @@ static void kvm_tlb_flush_vmid(struct kvm *kvm)
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kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);
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}
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static void kvm_set_pte(pte_t *pte, pte_t new_pte)
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{
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pte_val(*pte) = new_pte;
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/*
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* flush_pmd_entry just takes a void pointer and cleans the necessary
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* cache entries, so we can reuse the function for ptes.
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*/
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flush_pmd_entry(pte);
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}
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static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
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int min, int max)
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{
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@ -290,7 +278,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
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VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
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memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
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clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
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kvm_clean_pgd(pgd);
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kvm->arch.pgd = pgd;
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return 0;
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@ -422,22 +410,22 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
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return 0; /* ignore calls from kvm_set_spte_hva */
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pmd = mmu_memory_cache_alloc(cache);
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pud_populate(NULL, pud, pmd);
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pmd += pmd_index(addr);
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get_page(virt_to_page(pud));
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} else
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pmd = pmd_offset(pud, addr);
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}
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pmd = pmd_offset(pud, addr);
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/* Create 2nd stage page table mapping - Level 2 */
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if (pmd_none(*pmd)) {
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if (!cache)
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return 0; /* ignore calls from kvm_set_spte_hva */
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pte = mmu_memory_cache_alloc(cache);
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clean_pte_table(pte);
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kvm_clean_pte(pte);
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pmd_populate_kernel(NULL, pmd, pte);
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pte += pte_index(addr);
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get_page(virt_to_page(pmd));
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} else
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pte = pte_offset_kernel(pmd, addr);
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}
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pte = pte_offset_kernel(pmd, addr);
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if (iomap && pte_present(*pte))
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return -EFAULT;
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@ -473,7 +461,8 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
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pfn = __phys_to_pfn(pa);
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for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
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pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE | L_PTE_S2_RDWR);
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pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
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kvm_set_s2pte_writable(&pte);
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ret = mmu_topup_memory_cache(&cache, 2, 2);
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if (ret)
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@ -492,29 +481,6 @@ out:
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return ret;
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}
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static void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
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{
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/*
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* If we are going to insert an instruction page and the icache is
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* either VIPT or PIPT, there is a potential problem where the host
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* (or another VM) may have used the same page as this guest, and we
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* read incorrect data from the icache. If we're using a PIPT cache,
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* we can invalidate just that page, but if we are using a VIPT cache
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* we need to invalidate the entire icache - damn shame - as written
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* in the ARM ARM (DDI 0406C.b - Page B3-1393).
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*
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* VIVT caches are tagged using both the ASID and the VMID and doesn't
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* need any kind of flushing (DDI 0406C.b - Page B3-1392).
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*/
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if (icache_is_pipt()) {
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unsigned long hva = gfn_to_hva(kvm, gfn);
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__cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
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} else if (!icache_is_vivt_asid_tagged()) {
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/* any kind of VIPT cache */
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__flush_icache_all();
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}
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}
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static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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gfn_t gfn, struct kvm_memory_slot *memslot,
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unsigned long fault_status)
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@ -560,7 +526,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
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if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
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goto out_unlock;
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if (writable) {
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pte_val(new_pte) |= L_PTE_S2_RDWR;
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kvm_set_s2pte_writable(&new_pte);
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kvm_set_pfn_dirty(pfn);
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}
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stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false);
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@ -774,7 +740,7 @@ void kvm_clear_hyp_idmap(void)
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pmd = pmd_offset(pud, addr);
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pud_clear(pud);
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clean_pmd_entry(pmd);
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kvm_clean_pmd_entry(pmd);
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pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK));
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} while (pgd++, addr = next, addr < end);
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}
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