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x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge

Hygon's PCI vendor ID is 0x1d94, and there are PCI devices
0x1450/0x1463/0x1464 for the host bridge on the Hygon Dhyana platform.
Add Hygon Dhyana support to the PCI and northbridge subsystems by using
the code path of AMD family 17h.

 [ bp: Massage commit message, sort local vars into reverse xmas tree
   order and move the amd_northbridges.num check up. ]

Signed-off-by: Pu Wen <puwen@hygon.cn>
Signed-off-by: Borislav Petkov <bp@suse.de>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>	# pci_ids.h
Cc: tglx@linutronix.de
Cc: mingo@redhat.com
Cc: hpa@zytor.com
Cc: x86@kernel.org
Cc: thomas.lendacky@amd.com
Cc: helgaas@kernel.org
Cc: linux-pci@vger.kernel.org
Link: https://lkml.kernel.org/r/5f8877bd413f2ea0833378dd5454df0720e1c0df.1537885177.git.puwen@hygon.cn
hifive-unleashed-5.1
Pu Wen 2018-09-25 22:46:11 +08:00 committed by Borislav Petkov
parent b7a5cb4f22
commit c6babb5806
3 changed files with 43 additions and 10 deletions

View File

@ -61,6 +61,21 @@ static const struct pci_device_id amd_nb_link_ids[] = {
{} {}
}; };
static const struct pci_device_id hygon_root_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
{}
};
const struct pci_device_id hygon_nb_misc_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
{}
};
static const struct pci_device_id hygon_nb_link_ids[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
{}
};
const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = { const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
{ 0x00, 0x18, 0x20 }, { 0x00, 0x18, 0x20 },
{ 0xff, 0x00, 0x20 }, { 0xff, 0x00, 0x20 },
@ -194,15 +209,24 @@ EXPORT_SYMBOL_GPL(amd_df_indirect_read);
int amd_cache_northbridges(void) int amd_cache_northbridges(void)
{ {
u16 i = 0; const struct pci_device_id *misc_ids = amd_nb_misc_ids;
struct amd_northbridge *nb; const struct pci_device_id *link_ids = amd_nb_link_ids;
const struct pci_device_id *root_ids = amd_root_ids;
struct pci_dev *root, *misc, *link; struct pci_dev *root, *misc, *link;
struct amd_northbridge *nb;
u16 i = 0;
if (amd_northbridges.num) if (amd_northbridges.num)
return 0; return 0;
if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
root_ids = hygon_root_ids;
misc_ids = hygon_nb_misc_ids;
link_ids = hygon_nb_link_ids;
}
misc = NULL; misc = NULL;
while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL) while ((misc = next_northbridge(misc, misc_ids)) != NULL)
i++; i++;
if (!i) if (!i)
@ -218,11 +242,11 @@ int amd_cache_northbridges(void)
link = misc = root = NULL; link = misc = root = NULL;
for (i = 0; i != amd_northbridges.num; i++) { for (i = 0; i != amd_northbridges.num; i++) {
node_to_amd_nb(i)->root = root = node_to_amd_nb(i)->root = root =
next_northbridge(root, amd_root_ids); next_northbridge(root, root_ids);
node_to_amd_nb(i)->misc = misc = node_to_amd_nb(i)->misc = misc =
next_northbridge(misc, amd_nb_misc_ids); next_northbridge(misc, misc_ids);
node_to_amd_nb(i)->link = link = node_to_amd_nb(i)->link = link =
next_northbridge(link, amd_nb_link_ids); next_northbridge(link, link_ids);
} }
if (amd_gart_present()) if (amd_gart_present())
@ -261,6 +285,7 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges);
*/ */
bool __init early_is_amd_nb(u32 device) bool __init early_is_amd_nb(u32 device)
{ {
const struct pci_device_id *misc_ids = amd_nb_misc_ids;
const struct pci_device_id *id; const struct pci_device_id *id;
u32 vendor = device & 0xffff; u32 vendor = device & 0xffff;
@ -268,8 +293,11 @@ bool __init early_is_amd_nb(u32 device)
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON) boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return false; return false;
if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
misc_ids = hygon_nb_misc_ids;
device >>= 16; device >>= 16;
for (id = amd_nb_misc_ids; id->vendor; id++) for (id = misc_ids; id->vendor; id++)
if (vendor == id->vendor && device == id->device) if (vendor == id->vendor && device == id->device)
return true; return true;
return false; return false;
@ -281,7 +309,8 @@ struct resource *amd_get_mmconfig_range(struct resource *res)
u64 base, msr; u64 base, msr;
unsigned int segn_busn_bits; unsigned int segn_busn_bits;
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return NULL; return NULL;
/* assume all cpus from fam10h have mmconfig */ /* assume all cpus from fam10h have mmconfig */

View File

@ -93,7 +93,8 @@ static int __init early_root_info_init(void)
vendor = id & 0xffff; vendor = id & 0xffff;
device = (id>>16) & 0xffff; device = (id>>16) & 0xffff;
if (vendor != PCI_VENDOR_ID_AMD) if (vendor != PCI_VENDOR_ID_AMD &&
vendor != PCI_VENDOR_ID_HYGON)
continue; continue;
if (hb_probes[i].device == device) { if (hb_probes[i].device == device) {
@ -390,7 +391,8 @@ static int __init pci_io_ecs_init(void)
static int __init amd_postcore_init(void) static int __init amd_postcore_init(void)
{ {
if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
return 0; return 0;
early_root_info_init(); early_root_info_init();

View File

@ -2561,6 +2561,8 @@
#define PCI_VENDOR_ID_AMAZON 0x1d0f #define PCI_VENDOR_ID_AMAZON 0x1d0f
#define PCI_VENDOR_ID_HYGON 0x1d94
#define PCI_VENDOR_ID_TEKRAM 0x1de1 #define PCI_VENDOR_ID_TEKRAM 0x1de1
#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29 #define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29