x86/pci, x86/amd_nb: Add Hygon Dhyana support to PCI and northbridge
Hygon's PCI vendor ID is 0x1d94, and there are PCI devices 0x1450/0x1463/0x1464 for the host bridge on the Hygon Dhyana platform. Add Hygon Dhyana support to the PCI and northbridge subsystems by using the code path of AMD family 17h. [ bp: Massage commit message, sort local vars into reverse xmas tree order and move the amd_northbridges.num check up. ] Signed-off-by: Pu Wen <puwen@hygon.cn> Signed-off-by: Borislav Petkov <bp@suse.de> Acked-by: Bjorn Helgaas <bhelgaas@google.com> # pci_ids.h Cc: tglx@linutronix.de Cc: mingo@redhat.com Cc: hpa@zytor.com Cc: x86@kernel.org Cc: thomas.lendacky@amd.com Cc: helgaas@kernel.org Cc: linux-pci@vger.kernel.org Link: https://lkml.kernel.org/r/5f8877bd413f2ea0833378dd5454df0720e1c0df.1537885177.git.puwen@hygon.cnhifive-unleashed-5.1
parent
b7a5cb4f22
commit
c6babb5806
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@ -61,6 +61,21 @@ static const struct pci_device_id amd_nb_link_ids[] = {
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{}
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{}
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};
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};
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static const struct pci_device_id hygon_root_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
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{}
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};
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const struct pci_device_id hygon_nb_misc_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
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{}
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};
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static const struct pci_device_id hygon_nb_link_ids[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
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{}
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};
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
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{ 0x00, 0x18, 0x20 },
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{ 0x00, 0x18, 0x20 },
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{ 0xff, 0x00, 0x20 },
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{ 0xff, 0x00, 0x20 },
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@ -194,15 +209,24 @@ EXPORT_SYMBOL_GPL(amd_df_indirect_read);
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int amd_cache_northbridges(void)
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int amd_cache_northbridges(void)
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{
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{
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u16 i = 0;
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const struct pci_device_id *misc_ids = amd_nb_misc_ids;
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struct amd_northbridge *nb;
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const struct pci_device_id *link_ids = amd_nb_link_ids;
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const struct pci_device_id *root_ids = amd_root_ids;
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struct pci_dev *root, *misc, *link;
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struct pci_dev *root, *misc, *link;
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struct amd_northbridge *nb;
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u16 i = 0;
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if (amd_northbridges.num)
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if (amd_northbridges.num)
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return 0;
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return 0;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
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root_ids = hygon_root_ids;
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misc_ids = hygon_nb_misc_ids;
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link_ids = hygon_nb_link_ids;
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}
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misc = NULL;
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misc = NULL;
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while ((misc = next_northbridge(misc, amd_nb_misc_ids)) != NULL)
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while ((misc = next_northbridge(misc, misc_ids)) != NULL)
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i++;
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i++;
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if (!i)
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if (!i)
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@ -218,11 +242,11 @@ int amd_cache_northbridges(void)
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link = misc = root = NULL;
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link = misc = root = NULL;
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for (i = 0; i != amd_northbridges.num; i++) {
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for (i = 0; i != amd_northbridges.num; i++) {
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node_to_amd_nb(i)->root = root =
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node_to_amd_nb(i)->root = root =
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next_northbridge(root, amd_root_ids);
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next_northbridge(root, root_ids);
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node_to_amd_nb(i)->misc = misc =
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node_to_amd_nb(i)->misc = misc =
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next_northbridge(misc, amd_nb_misc_ids);
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next_northbridge(misc, misc_ids);
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node_to_amd_nb(i)->link = link =
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node_to_amd_nb(i)->link = link =
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next_northbridge(link, amd_nb_link_ids);
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next_northbridge(link, link_ids);
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}
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}
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if (amd_gart_present())
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if (amd_gart_present())
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@ -261,6 +285,7 @@ EXPORT_SYMBOL_GPL(amd_cache_northbridges);
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*/
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*/
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bool __init early_is_amd_nb(u32 device)
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bool __init early_is_amd_nb(u32 device)
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{
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{
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const struct pci_device_id *misc_ids = amd_nb_misc_ids;
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const struct pci_device_id *id;
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const struct pci_device_id *id;
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u32 vendor = device & 0xffff;
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u32 vendor = device & 0xffff;
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@ -268,8 +293,11 @@ bool __init early_is_amd_nb(u32 device)
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boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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return false;
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return false;
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if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
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misc_ids = hygon_nb_misc_ids;
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device >>= 16;
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device >>= 16;
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for (id = amd_nb_misc_ids; id->vendor; id++)
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for (id = misc_ids; id->vendor; id++)
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if (vendor == id->vendor && device == id->device)
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if (vendor == id->vendor && device == id->device)
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return true;
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return true;
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return false;
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return false;
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@ -281,7 +309,8 @@ struct resource *amd_get_mmconfig_range(struct resource *res)
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u64 base, msr;
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u64 base, msr;
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unsigned int segn_busn_bits;
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unsigned int segn_busn_bits;
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
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boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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return NULL;
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return NULL;
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/* assume all cpus from fam10h have mmconfig */
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/* assume all cpus from fam10h have mmconfig */
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@ -93,7 +93,8 @@ static int __init early_root_info_init(void)
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vendor = id & 0xffff;
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vendor = id & 0xffff;
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device = (id>>16) & 0xffff;
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device = (id>>16) & 0xffff;
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if (vendor != PCI_VENDOR_ID_AMD)
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if (vendor != PCI_VENDOR_ID_AMD &&
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vendor != PCI_VENDOR_ID_HYGON)
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continue;
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continue;
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if (hb_probes[i].device == device) {
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if (hb_probes[i].device == device) {
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@ -390,7 +391,8 @@ static int __init pci_io_ecs_init(void)
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static int __init amd_postcore_init(void)
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static int __init amd_postcore_init(void)
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{
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{
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD)
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if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
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boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
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return 0;
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return 0;
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early_root_info_init();
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early_root_info_init();
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@ -2561,6 +2561,8 @@
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#define PCI_VENDOR_ID_AMAZON 0x1d0f
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#define PCI_VENDOR_ID_AMAZON 0x1d0f
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#define PCI_VENDOR_ID_HYGON 0x1d94
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#define PCI_VENDOR_ID_TEKRAM 0x1de1
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#define PCI_VENDOR_ID_TEKRAM 0x1de1
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#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
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#define PCI_DEVICE_ID_TEKRAM_DC290 0xdc29
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