drm: rcar-du: Add interlaced feature flag
Upcoming implementations of the R-Car DU have removed support for interlaced display pipelines. Provide a means to determine this based on the feature flags of the hardware configuration structs. Signed-off-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
This commit is contained in:
parent
c14f63abeb
commit
c6e3194a3b
|
@ -681,11 +681,25 @@ static void rcar_du_crtc_atomic_flush(struct drm_crtc *crtc,
|
|||
rcar_du_vsp_atomic_flush(rcrtc);
|
||||
}
|
||||
|
||||
enum drm_mode_status rcar_du_crtc_mode_valid(struct drm_crtc *crtc,
|
||||
const struct drm_display_mode *mode)
|
||||
{
|
||||
struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
|
||||
struct rcar_du_device *rcdu = rcrtc->group->dev;
|
||||
bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
|
||||
|
||||
if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
|
||||
return MODE_NO_INTERLACE;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
|
||||
.atomic_begin = rcar_du_crtc_atomic_begin,
|
||||
.atomic_flush = rcar_du_crtc_atomic_flush,
|
||||
.atomic_enable = rcar_du_crtc_atomic_enable,
|
||||
.atomic_disable = rcar_du_crtc_atomic_disable,
|
||||
.mode_valid = rcar_du_crtc_mode_valid,
|
||||
};
|
||||
|
||||
static void rcar_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
|
||||
|
|
|
@ -35,7 +35,8 @@
|
|||
static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
|
||||
.gen = 2,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -56,7 +57,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
|
|||
static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
|
||||
.gen = 2,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -75,7 +77,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
|
|||
|
||||
static const struct rcar_du_device_info rcar_du_r8a7779_info = {
|
||||
.gen = 2,
|
||||
.features = 0,
|
||||
.features = RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -96,7 +98,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
|
|||
static const struct rcar_du_device_info rcar_du_r8a7790_info = {
|
||||
.gen = 2,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.quirks = RCAR_DU_QUIRK_ALIGN_128B,
|
||||
.channels_mask = BIT(2) | BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
|
@ -124,7 +127,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
|
|||
static const struct rcar_du_device_info rcar_du_r8a7791_info = {
|
||||
.gen = 2,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -146,7 +150,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
|
|||
static const struct rcar_du_device_info rcar_du_r8a7792_info = {
|
||||
.gen = 2,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/* R8A7792 has two RGB outputs. */
|
||||
|
@ -164,7 +169,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
|
|||
static const struct rcar_du_device_info rcar_du_r8a7794_info = {
|
||||
.gen = 2,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS,
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -186,7 +192,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
|
|||
.gen = 3,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE,
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -218,7 +225,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
|
|||
.gen = 3,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE,
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(2) | BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -246,7 +254,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
|
|||
.gen = 3,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE,
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(3) | BIT(1) | BIT(0),
|
||||
.routes = {
|
||||
/*
|
||||
|
@ -274,7 +283,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
|
|||
.gen = 3,
|
||||
.features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
|
||||
| RCAR_DU_FEATURE_EXT_CTRL_REGS
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE,
|
||||
| RCAR_DU_FEATURE_VSP1_SOURCE
|
||||
| RCAR_DU_FEATURE_INTERLACED,
|
||||
.channels_mask = BIT(0),
|
||||
.routes = {
|
||||
/* R8A77970 has one RGB output and one LVDS output. */
|
||||
|
|
|
@ -26,6 +26,7 @@ struct rcar_du_device;
|
|||
#define RCAR_DU_FEATURE_CRTC_IRQ_CLOCK BIT(0) /* Per-CRTC IRQ and clock */
|
||||
#define RCAR_DU_FEATURE_EXT_CTRL_REGS BIT(1) /* Has extended control registers */
|
||||
#define RCAR_DU_FEATURE_VSP1_SOURCE BIT(2) /* Has inputs from VSP1 */
|
||||
#define RCAR_DU_FEATURE_INTERLACED BIT(3) /* HW supports interlaced */
|
||||
|
||||
#define RCAR_DU_QUIRK_ALIGN_128B BIT(0) /* Align pitches to 128 bytes */
|
||||
|
||||
|
|
Loading…
Reference in a new issue