arch/tile: Various cleanups.
This change rolls up random cleanups not representing any actual bugs. - Remove a stale CONFIG_ value from the default tile_defconfig - Remove unused tns_atomic_xxx() family of methods from <asm/atomic.h> - Optimize get_order() using Tile's "clz" instruction - Fix a bad hypervisor upcall name (not currently used in Linux anyway) - Use __copy_in_user_inatomic() name for consistency, and export it - Export some additional hypervisor driver I/O upcalls and some homecache calls - Remove the obfuscating MEMCPY_TEST_WH64 support code - Other stray comment cleanups, #if 0 removal, etc. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>hifive-unleashed-5.1
Chris Metcalf
parent
1fcbe027b5
commit
c745a8a11f
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@ -231,7 +231,6 @@ CONFIG_HARDWALL=y
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CONFIG_MEMPROF=y
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CONFIG_XGBE=y
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CONFIG_NET_TILE=y
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CONFIG_PSEUDO_NAPI=y
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CONFIG_TILEPCI_ENDP=y
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CONFIG_TILEPCI_HOST_SUBSET=m
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CONFIG_TILE_IDE_GPIO=y
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@ -255,43 +255,6 @@ static inline void atomic64_set(atomic64_t *v, u64 n)
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#define smp_mb__after_atomic_dec() do { } while (0)
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#define smp_mb__after_atomic_inc() do { } while (0)
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/*
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* Support "tns" atomic integers. These are atomic integers that can
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* hold any value but "1". They are more efficient than regular atomic
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* operations because the "lock" (aka acquire) step is a single "tns"
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* in the uncontended case, and the "unlock" (aka release) step is a
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* single "store" without an mf. (However, note that on tilepro the
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* "tns" will evict the local cache line, so it's not all upside.)
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*
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* Note that you can ONLY observe the value stored in the pointer
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* using these operations; a direct read of the value may confusingly
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* return the special value "1".
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*/
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int __tns_atomic_acquire(atomic_t *);
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void __tns_atomic_release(atomic_t *p, int v);
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static inline void tns_atomic_set(atomic_t *v, int i)
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{
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__tns_atomic_acquire(v);
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__tns_atomic_release(v, i);
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}
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static inline int tns_atomic_cmpxchg(atomic_t *v, int o, int n)
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{
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int ret = __tns_atomic_acquire(v);
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__tns_atomic_release(v, (ret == o) ? n : ret);
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return ret;
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}
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static inline int tns_atomic_xchg(atomic_t *v, int n)
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{
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int ret = __tns_atomic_acquire(v);
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__tns_atomic_release(v, n);
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return ret;
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}
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#endif /* !__ASSEMBLY__ */
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/*
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@ -129,6 +129,11 @@ static inline u64 pmd_val(pmd_t pmd)
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#endif
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static inline __attribute_const__ int get_order(unsigned long size)
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{
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return BITS_PER_LONG - __builtin_clzl((size - 1) >> PAGE_SHIFT);
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}
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#endif /* !__ASSEMBLY__ */
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#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
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@ -332,7 +337,6 @@ extern pte_t *virt_to_pte(struct mm_struct *mm, unsigned long addr);
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(VM_READ | VM_WRITE | VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
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#include <asm-generic/memory_model.h>
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#include <asm-generic/getorder.h>
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#endif /* __KERNEL__ */
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@ -389,14 +389,14 @@ static inline unsigned long __must_check copy_from_user(void *to,
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* Returns number of bytes that could not be copied.
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* On success, this will be zero.
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*/
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extern unsigned long __copy_in_user_asm(
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extern unsigned long __copy_in_user_inatomic(
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void __user *to, const void __user *from, unsigned long n);
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static inline unsigned long __must_check
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__copy_in_user(void __user *to, const void __user *from, unsigned long n)
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{
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might_sleep();
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return __copy_in_user_asm(to, from, n);
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return __copy_in_user_inatomic(to, from, n);
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}
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static inline unsigned long __must_check
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@ -532,11 +532,11 @@ void hv_disable_intr(HV_IntrMask disab_mask);
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*/
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void hv_clear_intr(HV_IntrMask clear_mask);
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/** Assert a set of device interrupts.
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/** Raise a set of device interrupts.
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*
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* @param assert_mask Bitmap of interrupts to clear.
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* @param raise_mask Bitmap of interrupts to raise.
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*/
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void hv_assert_intr(HV_IntrMask assert_mask);
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void hv_raise_intr(HV_IntrMask raise_mask);
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/** Trigger a one-shot interrupt on some tile
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*
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@ -1712,7 +1712,7 @@ typedef struct
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* @param cache_control This argument allows you to specify a length of
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* physical address space to flush (maximum HV_FLUSH_MAX_CACHE_LEN).
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* You can "or" in HV_FLUSH_EVICT_L2 to flush the whole L2 cache.
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* You can "or" in HV_FLUSH_EVICT_LI1 to flush the whole LII cache.
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* You can "or" in HV_FLUSH_EVICT_L1I to flush the whole L1I cache.
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* HV_FLUSH_ALL flushes all caches.
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* @param cache_cpumask Bitmask (in row-major order, supervisor-relative) of
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* tile indices to perform cache flush on. The low bit of the first
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@ -7,7 +7,9 @@ lib-y = cacheflush.o checksum.o cpumask.o delay.o \
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memcpy_$(BITS).o memchr_$(BITS).o memmove_$(BITS).o memset_$(BITS).o \
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strchr_$(BITS).o strlen_$(BITS).o
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ifneq ($(CONFIG_TILEGX),y)
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ifeq ($(CONFIG_TILEGX),y)
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lib-y += memcpy_user_64.o
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else
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lib-y += atomic_32.o atomic_asm_32.o memcpy_tile64.o
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endif
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@ -36,21 +36,29 @@ EXPORT_SYMBOL(clear_user_asm);
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EXPORT_SYMBOL(current_text_addr);
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EXPORT_SYMBOL(dump_stack);
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/* arch/tile/lib/__memcpy.S */
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/* NOTE: on TILE64, these symbols appear in arch/tile/lib/memcpy_tile64.c */
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/* arch/tile/lib/, various memcpy files */
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EXPORT_SYMBOL(memcpy);
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EXPORT_SYMBOL(__copy_to_user_inatomic);
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EXPORT_SYMBOL(__copy_from_user_inatomic);
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EXPORT_SYMBOL(__copy_from_user_zeroing);
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#ifdef __tilegx__
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EXPORT_SYMBOL(__copy_in_user_inatomic);
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#endif
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/* hypervisor glue */
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#include <hv/hypervisor.h>
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EXPORT_SYMBOL(hv_dev_open);
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EXPORT_SYMBOL(hv_dev_pread);
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EXPORT_SYMBOL(hv_dev_pwrite);
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EXPORT_SYMBOL(hv_dev_preada);
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EXPORT_SYMBOL(hv_dev_pwritea);
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EXPORT_SYMBOL(hv_dev_poll);
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EXPORT_SYMBOL(hv_dev_poll_cancel);
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EXPORT_SYMBOL(hv_dev_close);
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EXPORT_SYMBOL(hv_sysconf);
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EXPORT_SYMBOL(hv_confstr);
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/* -ltile-cc */
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/* libgcc.a */
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uint32_t __udivsi3(uint32_t dividend, uint32_t divisor);
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EXPORT_SYMBOL(__udivsi3);
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int32_t __divsi3(int32_t dividend, int32_t divisor);
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@ -70,8 +78,6 @@ EXPORT_SYMBOL(__moddi3);
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#ifndef __tilegx__
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uint64_t __ll_mul(uint64_t n0, uint64_t n1);
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EXPORT_SYMBOL(__ll_mul);
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#endif
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#ifndef __tilegx__
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int64_t __muldi3(int64_t, int64_t);
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EXPORT_SYMBOL(__muldi3);
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uint64_t __lshrdi3(uint64_t, unsigned int);
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@ -17,10 +17,6 @@
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#include <arch/chip.h>
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#if CHIP_HAS_WH64() || defined(MEMCPY_TEST_WH64)
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#define MEMCPY_USE_WH64
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#endif
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#include <linux/linkage.h>
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@ -160,7 +156,7 @@ EX: { sw r0, r3; addi r0, r0, 4; addi r2, r2, -4 }
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{ addi r3, r1, 60; andi r9, r9, -64 }
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#ifdef MEMCPY_USE_WH64
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#if CHIP_HAS_WH64()
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/* No need to prefetch dst, we'll just do the wh64
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* right before we copy a line.
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*/
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@ -173,7 +169,7 @@ EX: { lw r6, r3; addi r3, r3, 64 }
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/* Intentionally stall for a few cycles to leave L2 cache alone. */
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{ bnzt zero, . }
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EX: { lw r7, r3; addi r3, r3, 64 }
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#ifndef MEMCPY_USE_WH64
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#if !CHIP_HAS_WH64()
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/* Prefetch the dest */
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/* Intentionally stall for a few cycles to leave L2 cache alone. */
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{ bnzt zero, . }
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@ -288,15 +284,7 @@ EX: { lw r7, r3; addi r3, r3, 64 }
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/* Fill second L1D line. */
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EX: { lw r17, r17; addi r1, r1, 48; mvz r3, r13, r1 } /* r17 = WORD_4 */
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#ifdef MEMCPY_TEST_WH64
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/* Issue a fake wh64 that clobbers the destination words
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* with random garbage, for testing.
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*/
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{ movei r19, 64; crc32_32 r10, r2, r9 }
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.Lwh64_test_loop:
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EX: { sw r9, r10; addi r9, r9, 4; addi r19, r19, -4 }
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{ bnzt r19, .Lwh64_test_loop; crc32_32 r10, r10, r19 }
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#elif CHIP_HAS_WH64()
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#if CHIP_HAS_WH64()
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/* Prepare destination line for writing. */
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EX: { wh64 r9; addi r9, r9, 64 }
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#else
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@ -340,7 +328,7 @@ EX: { lw r18, r1; addi r1, r1, 4 } /* r18 = WORD_8 */
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EX: { sw r0, r16; addi r0, r0, 4; add r16, r0, r2 } /* store(WORD_0) */
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EX: { sw r0, r13; addi r0, r0, 4; andi r16, r16, -64 } /* store(WORD_1) */
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EX: { sw r0, r14; addi r0, r0, 4; slt_u r16, r9, r16 } /* store(WORD_2) */
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#ifdef MEMCPY_USE_WH64
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#if CHIP_HAS_WH64()
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EX: { sw r0, r15; addi r0, r0, 4; addi r13, sp, -64 } /* store(WORD_3) */
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#else
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/* Back up the r9 to a cache line we are already storing to
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@ -141,7 +141,6 @@ void *memset(void *s, int c, size_t n)
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*/
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__insn_prefetch(&out32[ahead32]);
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#if 1
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#if CACHE_LINE_SIZE_IN_WORDS % 4 != 0
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#error "Unhandled CACHE_LINE_SIZE_IN_WORDS"
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#endif
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@ -157,30 +156,6 @@ void *memset(void *s, int c, size_t n)
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*out32++ = v32;
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*out32++ = v32;
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}
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#else
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/* Unfortunately, due to a code generator flaw this
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* allocates a separate register for each of these
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* stores, which requires a large number of spills,
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* which makes this procedure enormously bigger
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* (something like 70%)
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*/
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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*out32++ = v32;
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n32 -= 16;
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#endif
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/* To save compiled code size, reuse this loop even
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* when we run out of prefetching to do by dropping
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@ -567,6 +567,14 @@ do_sigbus:
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* since that might indicate we have not yet squirreled the SPR
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* contents away and can thus safely take a recursive interrupt.
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* Accordingly, the hypervisor passes us the PC via SYSTEM_SAVE_1_2.
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*
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* Note that this routine is called before homecache_tlb_defer_enter(),
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* which means that we can properly unlock any atomics that might
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* be used there (good), but also means we must be very sensitive
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* to not touch any data structures that might be located in memory
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* that could migrate, as we could be entering the kernel on a dataplane
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* cpu that has been deferring kernel TLB updates. This means, for
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* example, that we can't migrate init_mm or its pgd.
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*/
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struct intvec_state do_page_fault_ics(struct pt_regs *regs, int fault_num,
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unsigned long address,
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@ -29,6 +29,7 @@
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#include <linux/timex.h>
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#include <linux/cache.h>
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#include <linux/smp.h>
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#include <linux/module.h>
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#include <asm/page.h>
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#include <asm/sections.h>
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@ -348,6 +349,7 @@ pte_t pte_set_home(pte_t pte, int home)
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return pte;
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}
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EXPORT_SYMBOL(pte_set_home);
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/*
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* The routines in this section are the "static" versions of the normal
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@ -403,6 +405,7 @@ struct page *homecache_alloc_pages(gfp_t gfp_mask,
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homecache_change_page_home(page, order, home);
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return page;
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}
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EXPORT_SYMBOL(homecache_alloc_pages);
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struct page *homecache_alloc_pages_node(int nid, gfp_t gfp_mask,
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unsigned int order, int home)
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