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clk: socfpga: stratix10: fix rate caclulationg for cnt_clks 

Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.

Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
alistair/sunxi64-5.4-dsi
Dinh Nguyen 2019-08-14 10:30:14 -05:00 committed by Stephen Boyd
parent baf7b79e1a
commit c7ec75ea4d
1 changed files with 1 additions and 1 deletions
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2
drivers/clk/socfpga/clk-periph-s10.c
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@ -38,7 +38,7 @@ static unsigned long clk_peri_cnt_clk_recalc_rate(struct clk_hw *hwclk,
if (socfpgaclk->fixed_div) {
div = socfpgaclk->fixed_div;
} else {
if (!socfpgaclk->bypass_reg)
if (socfpgaclk->hw.reg)
div = ((readl(socfpgaclk->hw.reg) & 0x7ff) + 1);
}