diff --git a/drivers/staging/media/imx/imx8-isi-hw.c b/drivers/staging/media/imx/imx8-isi-hw.c
index 4d8b18adfd42..ceedfc282305 100644
--- a/drivers/staging/media/imx/imx8-isi-hw.c
+++ b/drivers/staging/media/imx/imx8-isi-hw.c
@@ -3,7 +3,6 @@
  * Copyright (c) 2019 NXP Semiconductor
  *
  */
-
 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
 
 #include "imx8-isi-hw.h"
@@ -17,56 +16,56 @@ void dump_isi_regs(struct mxc_isi_dev *mxc_isi)
 	struct device *dev = &mxc_isi->pdev->dev;
 	struct {
 		u32 offset;
-		const char *const name[64];
+		const char *const name;
 	} registers[] = {
-		{ 0x00h, "CHNL_CTRL" },
-		{ 0x04h, "CHNL_IMG_CTRL" },
-		{ 0x08h, "CHNL_OUT_BUF_CTRL" },
-		{ 0x0Ch, "CHNL_IMG_CFG" },
-		{ 0x10h, "CHNL_IER" },
-		{ 0x14h, "CHNL_STS" },
-		{ 0x18h, "CHNL_SCALE_FACTOR" },
-		{ 0x1Ch, "CHNL_SCALE_OFFSET" },
-		{ 0x20h, "CHNL_CROP_ULC" },
-		{ 0x24h, "CHNL_CROP_LRC" },
-		{ 0x28h, "CHNL_CSC_COEFF0" },
-		{ 0x2Ch, "CHNL_CSC_COEFF1" },
-		{ 0x30h, "CHNL_CSC_COEFF2" },
-		{ 0x34h, "CHNL_CSC_COEFF3" },
-		{ 0x38h, "CHNL_CSC_COEFF4" },
-		{ 0x3Ch, "CHNL_CSC_COEFF5" },
-		{ 0x40h, "CHNL_ROI_0_ALPHA" },
-		{ 0x44h, "CHNL_ROI_0_ULC" },
-		{ 0x48h, "CHNL_ROI_0_LRC" },
-		{ 0x4Ch, "CHNL_ROI_1_ALPHA" },
-		{ 0x50h, "CHNL_ROI_1_ULC" },
-		{ 0x54h, "CHNL_ROI_1_LRC" },
-		{ 0x58h, "CHNL_ROI_2_ALPHA" },
-		{ 0x5Ch, "CHNL_ROI_2_ULC" },
-		{ 0x60h, "CHNL_ROI_2_LRC" },
-		{ 0x64h, "CHNL_ROI_3_ALPHA" },
-		{ 0x68h, "CHNL_ROI_3_ULC" },
-		{ 0x6Ch, "CHNL_ROI_3_LRC" },
-		{ 0x70h, "CHNL_OUT_BUF1_ADDR_Y" },
-		{ 0x74h, "CHNL_OUT_BUF1_ADDR_U" },
-		{ 0x78h, "CHNL_OUT_BUF1_ADDR_V" },
-		{ 0x7Ch, "CHNL_OUT_BUF_PITCH" },
-		{ 0x80h, "CHNL_IN_BUF_ADDR" },
-		{ 0x84h, "CHNL_IN_BUF_PITCH" },
-		{ 0x88h, "CHNL_MEM_RD_CTRL" },
-		{ 0x8Ch, "CHNL_OUT_BUF2_ADDR_Y" },
-		{ 0x90h, "CHNL_OUT_BUF2_ADDR_U" },
-		{ 0x94h, "CHNL_OUT_BUF2_ADDR_V" },
-		{ 0x98h, "CHNL_SCL_IMG_CFG" },
-		{ 0x9Ch, "CHNL_FLOW_CTRL" },
+		{ 0x00, "CHNL_CTRL" },
+		{ 0x04, "CHNL_IMG_CTRL" },
+		{ 0x08, "CHNL_OUT_BUF_CTRL" },
+		{ 0x0C, "CHNL_IMG_CFG" },
+		{ 0x10, "CHNL_IER" },
+		{ 0x14, "CHNL_STS" },
+		{ 0x18, "CHNL_SCALE_FACTOR" },
+		{ 0x1C, "CHNL_SCALE_OFFSET" },
+		{ 0x20, "CHNL_CROP_ULC" },
+		{ 0x24, "CHNL_CROP_LRC" },
+		{ 0x28, "CHNL_CSC_COEFF0" },
+		{ 0x2C, "CHNL_CSC_COEFF1" },
+		{ 0x30, "CHNL_CSC_COEFF2" },
+		{ 0x34, "CHNL_CSC_COEFF3" },
+		{ 0x38, "CHNL_CSC_COEFF4" },
+		{ 0x3C, "CHNL_CSC_COEFF5" },
+		{ 0x40, "CHNL_ROI_0_ALPHA" },
+		{ 0x44, "CHNL_ROI_0_ULC" },
+		{ 0x48, "CHNL_ROI_0_LRC" },
+		{ 0x4C, "CHNL_ROI_1_ALPHA" },
+		{ 0x50, "CHNL_ROI_1_ULC" },
+		{ 0x54, "CHNL_ROI_1_LRC" },
+		{ 0x58, "CHNL_ROI_2_ALPHA" },
+		{ 0x5C, "CHNL_ROI_2_ULC" },
+		{ 0x60, "CHNL_ROI_2_LRC" },
+		{ 0x64, "CHNL_ROI_3_ALPHA" },
+		{ 0x68, "CHNL_ROI_3_ULC" },
+		{ 0x6C, "CHNL_ROI_3_LRC" },
+		{ 0x70, "CHNL_OUT_BUF1_ADDR_Y" },
+		{ 0x74, "CHNL_OUT_BUF1_ADDR_U" },
+		{ 0x78, "CHNL_OUT_BUF1_ADDR_V" },
+		{ 0x7C, "CHNL_OUT_BUF_PITCH" },
+		{ 0x80, "CHNL_IN_BUF_ADDR" },
+		{ 0x84, "CHNL_IN_BUF_PITCH" },
+		{ 0x88, "CHNL_MEM_RD_CTRL" },
+		{ 0x8C, "CHNL_OUT_BUF2_ADDR_Y" },
+		{ 0x90, "CHNL_OUT_BUF2_ADDR_U" },
+		{ 0x94, "CHNL_OUT_BUF2_ADDR_V" },
+		{ 0x98, "CHNL_SCL_IMG_CFG" },
+		{ 0x9C, "CHNL_FLOW_CTRL" },
 	};
 	u32 i;
 
 	dev_dbg(dev, "ISI CHNLC register dump, isi%d\n", mxc_isi->id);
 	for (i = 0; i < ARRAY_SIZE(registers); i++) {
-		u32 reg = readl(mxc_isi->regs + registers.offset);
+		u32 reg = readl(mxc_isi->regs + registers[i].offset);
 		dev_dbg(dev, "%20s[0x%.2x]: %.2x\n",
-			registers.name, registers.offset, reg);
+			registers[i].name, registers[i].offset, reg);
 	}
 }
 #else