drm/915: fix relaxed tiling on gen2: tile height
A tile on gen2 has a size of 2kb, stride of 128 bytes and 16 rows. Userspace was broken and assumed 8 rows. Chris Wilson noted that the kernel unfortunately can't reliable check that because libdrm rounds up the size to the next bucket. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Keith Packard <keithp@keithp.com>
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@ -1449,8 +1449,9 @@ i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj)
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* edge of an even tile row (where tile rows are counted as if the bo is
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* edge of an even tile row (where tile rows are counted as if the bo is
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* placed in a fenced gtt region).
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* placed in a fenced gtt region).
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*/
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*/
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if (IS_GEN2(dev) ||
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if (IS_GEN2(dev))
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(obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
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tile_height = 16;
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else if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
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tile_height = 32;
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tile_height = 32;
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else
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else
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tile_height = 8;
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tile_height = 8;
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