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drm/i915: Inline set_base into crtc_mode_set

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A lot of the code in set_base is uncessary when the crtc is off, so we
can get rid of it all. Also, we don't need to call the fbc/psr update
functions since the crtc enable/disable hooks do that already.

The only things we really need are:
- Pin the new framebuffer and potentially unpin the old framebuffer
  (if the crtc has been on and we only change the configuration).
- Update the plane registers.

The first step will move out of platform code with the very next
patch.

v2: Don't forget about haswell ...

Reviewed-by: Akash Goel <akash.goel@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Daniel Vetter 2014-04-24 23:55:04 +02:00
parent 71b1c373ca
commit c8f7a0dbd7
1 changed files with 63 additions and 6 deletions
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69
drivers/gpu/drm/i915/intel_display.c
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@ -5771,6 +5771,7 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
bool is_lvds = false, is_dsi = false;
struct intel_encoder *encoder;
const intel_limit_t *limit;
struct drm_framebuffer *old_fb;
int ret;
for_each_encoder_on_crtc(dev, crtc, encoder) {
@ -5871,9 +5872,27 @@ skip_dpll:
I915_WRITE(DSPCNTR(plane), dspcntr);
POSTING_READ(DSPCNTR(plane));
ret = intel_pipe_set_base(crtc, x, y, fb);
mutex_lock(&dev->struct_mutex);
ret = intel_pin_and_fence_fb_obj(dev,
to_intel_framebuffer(fb)->obj,
NULL);
if (ret != 0) {
DRM_ERROR("pin & fence failed\n");
mutex_unlock(&dev->struct_mutex);
return ret;
}
old_fb = crtc->primary->fb;
if (old_fb)
intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
mutex_unlock(&dev->struct_mutex);
return ret;
dev_priv->display.update_primary_plane(crtc, fb, x, y);
crtc->primary->fb = fb;
crtc->x = x;
crtc->y = y;
return 0;
}
static void i9xx_get_pfit_config(struct intel_crtc *crtc,
@ -6809,6 +6828,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
bool is_lvds = false;
struct intel_encoder *encoder;
struct intel_shared_dpll *pll;
struct drm_framebuffer *old_fb;
int ret;
for_each_encoder_on_crtc(dev, crtc, encoder) {
@ -6886,9 +6906,27 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
POSTING_READ(DSPCNTR(plane));
ret = intel_pipe_set_base(crtc, x, y, fb);
mutex_lock(&dev->struct_mutex);
ret = intel_pin_and_fence_fb_obj(dev,
to_intel_framebuffer(fb)->obj,
NULL);
if (ret != 0) {
DRM_ERROR("pin & fence failed\n");
mutex_unlock(&dev->struct_mutex);
return ret;
}
old_fb = crtc->primary->fb;
if (old_fb)
intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
mutex_unlock(&dev->struct_mutex);
return ret;
dev_priv->display.update_primary_plane(crtc, fb, x, y);
crtc->primary->fb = fb;
crtc->x = x;
crtc->y = y;
return 0;
}
static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
@ -7358,6 +7396,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int plane = intel_crtc->plane;
struct drm_framebuffer *old_fb;
int ret;
if (!intel_ddi_pll_select(intel_crtc))
@ -7384,9 +7423,27 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
POSTING_READ(DSPCNTR(plane));
ret = intel_pipe_set_base(crtc, x, y, fb);
mutex_lock(&dev->struct_mutex);
ret = intel_pin_and_fence_fb_obj(dev,
to_intel_framebuffer(fb)->obj,
NULL);
if (ret != 0) {
DRM_ERROR("pin & fence failed\n");
mutex_unlock(&dev->struct_mutex);
return ret;
}
old_fb = crtc->primary->fb;
if (old_fb)
intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
mutex_unlock(&dev->struct_mutex);
return ret;
dev_priv->display.update_primary_plane(crtc, fb, x, y);
crtc->primary->fb = fb;
crtc->x = x;
crtc->y = y;
return 0;
}
static bool haswell_get_pipe_config(struct intel_crtc *crtc,