drm/i915/chv: Determine CHV slice/subslice/EU info
Total EU was already being detected on CHV, so we just add the additional info parameters. The detection method is changed to be more robust in the case of subslice fusing - we don't want to trust the EU fuse bits corresponding to subslices which are fused-off. v2: Fixed subslice disable bitmasks and removed unnecessary ? operation (Ville) Signed-off-by: Jeff McGee <jeff.mcgee@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -611,14 +611,42 @@ static void intel_device_info_runtime_init(struct drm_device *dev)
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/* Initialize slice/subslice/EU info */
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if (IS_CHERRYVIEW(dev)) {
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u32 fuse, mask_eu;
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u32 fuse, eu_dis;
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fuse = I915_READ(CHV_FUSE_GT);
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mask_eu = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
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CHV_FGT_EU_DIS_SS0_R1_MASK |
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CHV_FGT_EU_DIS_SS1_R0_MASK |
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CHV_FGT_EU_DIS_SS1_R1_MASK);
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info->eu_total = 16 - hweight32(mask_eu);
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info->slice_total = 1;
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if (!(fuse & CHV_FGT_DISABLE_SS0)) {
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info->subslice_per_slice++;
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eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
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CHV_FGT_EU_DIS_SS0_R1_MASK);
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info->eu_total += 8 - hweight32(eu_dis);
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}
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if (!(fuse & CHV_FGT_DISABLE_SS1)) {
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info->subslice_per_slice++;
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eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
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CHV_FGT_EU_DIS_SS1_R1_MASK);
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info->eu_total += 8 - hweight32(eu_dis);
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}
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info->subslice_total = info->subslice_per_slice;
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/*
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* CHV expected to always have a uniform distribution of EU
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* across subslices.
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*/
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info->eu_per_subslice = info->subslice_total ?
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info->eu_total / info->subslice_total :
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0;
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/*
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* CHV supports subslice power gating on devices with more than
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* one subslice, and supports EU power gating on devices with
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* more than one EU pair per subslice.
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*/
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info->has_slice_pg = 0;
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info->has_subslice_pg = (info->subslice_total > 1);
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info->has_eu_pg = (info->eu_per_subslice > 2);
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} else if (IS_SKYLAKE(dev)) {
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const int s_max = 3, ss_max = 4, eu_max = 8;
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int s, ss;
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@ -1522,6 +1522,8 @@ enum skl_disp_power_wells {
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/* Fuse readout registers for GT */
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#define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168)
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#define CHV_FGT_DISABLE_SS0 (1 << 10)
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#define CHV_FGT_DISABLE_SS1 (1 << 11)
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#define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16
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#define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT)
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#define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20
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