drm/nouveau/gr/gf100: add support for securely-managed falcons
Start securely-managed falcons using secboot functions since the process for them is different from just writing CPUCTL. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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@ -28,6 +28,7 @@
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#include <core/client.h>
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#include <core/option.h>
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#include <core/firmware.h>
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#include <subdev/secboot.h>
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#include <subdev/fb.h>
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#include <subdev/mc.h>
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#include <subdev/pmu.h>
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@ -1428,21 +1429,40 @@ gf100_gr_init_ctxctl(struct gf100_gr *gr)
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const struct gf100_grctx_func *grctx = gr->func->grctx;
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struct nvkm_subdev *subdev = &gr->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_secboot *sb = device->secboot;
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int i;
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if (gr->firmware) {
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/* load fuc microcode */
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nvkm_mc_unk260(device->mc, 0);
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gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c, &gr->fuc409d);
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gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac, &gr->fuc41ad);
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/* securely-managed falcons must be reset using secure boot */
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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gf100_gr_init_fw(gr, 0x409000, &gr->fuc409c,
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&gr->fuc409d);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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nvkm_secboot_reset(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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gf100_gr_init_fw(gr, 0x41a000, &gr->fuc41ac,
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&gr->fuc41ad);
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nvkm_mc_unk260(device->mc, 1);
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/* start both of them running */
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nvkm_wr32(device, 0x409840, 0xffffffff);
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nvkm_wr32(device, 0x41a10c, 0x00000000);
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nvkm_wr32(device, 0x40910c, 0x00000000);
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nvkm_wr32(device, 0x41a100, 0x00000002);
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nvkm_wr32(device, 0x409100, 0x00000002);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_GPCCS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_GPCCS);
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else
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nvkm_wr32(device, 0x41a100, 0x00000002);
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if (nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_FECS))
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nvkm_secboot_start(sb, NVKM_SECBOOT_FALCON_FECS);
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else
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nvkm_wr32(device, 0x409100, 0x00000002);
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if (nvkm_msec(device, 2000,
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if (nvkm_rd32(device, 0x409800) & 0x00000001)
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break;
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