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Merge branch 'rmk-devel-mxc-pu-v2' of git://pasiphae.extern.pengutronix.de/git/imx/linux-2.6 into devel

hifive-unleashed-5.1
Russell King 2008-12-17 20:05:39 +00:00 committed by Russell King
parent c613bbba6f 47fee6fedd
commit c95a44329e
46 changed files with 3890 additions and 366 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/Makefile
View File

@ -139,6 +139,7 @@ endif
plat-$(CONFIG_ARCH_MXC) := mxc
machine-$(CONFIG_ARCH_MX2) := mx2
machine-$(CONFIG_ARCH_MX3) := mx3
machine-$(CONFIG_ARCH_MX1) := mx1
machine-$(CONFIG_ARCH_ORION5X) := orion5x
plat-$(CONFIG_PLAT_ORION) := orion
machine-$(CONFIG_ARCH_MSM) := msm

790
arch/arm/configs/mx31moboard_defconfig 100644
View File

@ -0,0 +1,790 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.27-rc5
# Fri Oct 24 11:41:22 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_SUPPORTS_AOUT=y
CONFIG_ZONE_DMA=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
CONFIG_EXPERIMENTAL=y
CONFIG_BROKEN_ON_SMP=y
CONFIG_LOCK_KERNEL=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
CONFIG_LOCALVERSION_AUTO=y
CONFIG_SWAP=y
CONFIG_SYSVIPC=y
CONFIG_SYSVIPC_SYSCTL=y
# CONFIG_POSIX_MQUEUE is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
# CONFIG_CGROUPS is not set
CONFIG_GROUP_SCHED=y
CONFIG_FAIR_GROUP_SCHED=y
# CONFIG_RT_GROUP_SCHED is not set
CONFIG_USER_SCHED=y
# CONFIG_CGROUP_SCHED is not set
CONFIG_SYSFS_DEPRECATED=y
CONFIG_SYSFS_DEPRECATED_V2=y
# CONFIG_RELAY is not set
# CONFIG_NAMESPACES is not set
# CONFIG_BLK_DEV_INITRD is not set
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL=y
CONFIG_EMBEDDED=y
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
CONFIG_COMPAT_BRK=y
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLAB=y
# CONFIG_SLUB is not set
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
# CONFIG_KPROBES is not set
# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set
# CONFIG_HAVE_IOREMAP_PROT is not set
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
# CONFIG_HAVE_ARCH_TRACEHOOK is not set
# CONFIG_HAVE_DMA_ATTRS is not set
# CONFIG_USE_GENERIC_SMP_HELPERS is not set
# CONFIG_HAVE_CLK is not set
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
CONFIG_MODULES=y
# CONFIG_MODULE_FORCE_LOAD is not set
CONFIG_MODULE_UNLOAD=y
CONFIG_MODULE_FORCE_UNLOAD=y
CONFIG_MODVERSIONS=y
# CONFIG_MODULE_SRCVERSION_ALL is not set
CONFIG_KMOD=y
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
CONFIG_IOSCHED_AS=y
CONFIG_IOSCHED_DEADLINE=y
CONFIG_IOSCHED_CFQ=y
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
CONFIG_DEFAULT_CFQ=y
# CONFIG_DEFAULT_NOOP is not set
CONFIG_DEFAULT_IOSCHED="cfq"
CONFIG_CLASSIC_RCU=y
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
CONFIG_ARCH_MXC=y
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM7X00A is not set
#
# Boot options
#
#
# Power management
#
#
# Freescale MXC Implementations
#
# CONFIG_ARCH_MX2 is not set
CONFIG_ARCH_MX3=y
#
# MX3 Options
#
# CONFIG_MACH_MX31ADS is not set
# CONFIG_MACH_PCM037 is not set
# CONFIG_MACH_MX31LITE is not set
CONFIG_MACH_MX31MOBOARD=y
# CONFIG_MXC_IRQ_PRIOR is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V6=y
# CONFIG_CPU_32v6K is not set
CONFIG_CPU_32v6=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
CONFIG_TICK_ONESHOT=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_PREEMPT=y
CONFIG_HZ=100
CONFIG_AEABI=y
# CONFIG_OABI_COMPAT is not set
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
# CONFIG_ARCH_DISCONTIGMEM_ENABLE is not set
CONFIG_SELECT_MEMORY_MODEL=y
CONFIG_FLATMEM_MANUAL=y
# CONFIG_DISCONTIGMEM_MANUAL is not set
# CONFIG_SPARSEMEM_MANUAL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
# CONFIG_SPARSEMEM_STATIC is not set
# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
CONFIG_ZONE_DMA_FLAG=1
CONFIG_BOUNCE=y
CONFIG_VIRT_TO_BUS=y
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0x0
CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_CMDLINE="noinitrd console=ttymxc0,115200 root=/dev/mtdblock2 rw ip=off"
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
CONFIG_VFP=y
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
# CONFIG_NET_KEY is not set
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_ARPD is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
# CONFIG_INET_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_LRO is not set
# CONFIG_INET_DIAG is not set
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
# CONFIG_TCP_MD5SIG is not set
# CONFIG_IPV6 is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_IP_DCCP is not set
# CONFIG_IP_SCTP is not set
# CONFIG_TIPC is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_X25 is not set
# CONFIG_LAPB is not set
# CONFIG_ECONET is not set
# CONFIG_WAN_ROUTER is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_AF_RXRPC is not set
#
# Wireless
#
# CONFIG_CFG80211 is not set
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
# CONFIG_NET_9P is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
CONFIG_PREVENT_FIRMWARE_BUILD=y
CONFIG_FW_LOADER=m
CONFIG_FIRMWARE_IN_KERNEL=y
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
CONFIG_MTD=y
# CONFIG_MTD_DEBUG is not set
# CONFIG_MTD_CONCAT is not set
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_REDBOOT_PARTS=y
CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1
# CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED is not set
CONFIG_MTD_REDBOOT_PARTS_READONLY=y
# CONFIG_MTD_CMDLINE_PARTS is not set
# CONFIG_MTD_AFS_PARTS is not set
# CONFIG_MTD_AR7_PARTS is not set
#
# User Modules And Translation Layers
#
CONFIG_MTD_CHAR=y
CONFIG_MTD_BLKDEVS=y
CONFIG_MTD_BLOCK=y
# CONFIG_FTL is not set
# CONFIG_NFTL is not set
# CONFIG_INFTL is not set
# CONFIG_RFD_FTL is not set
# CONFIG_SSFDC is not set
# CONFIG_MTD_OOPS is not set
#
# RAM/ROM/Flash chip drivers
#
CONFIG_MTD_CFI=y
# CONFIG_MTD_JEDECPROBE is not set
CONFIG_MTD_GEN_PROBE=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_NOSWAP=y
# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set
# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set
CONFIG_MTD_CFI_GEOMETRY=y
# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set
CONFIG_MTD_MAP_BANK_WIDTH_2=y
# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
CONFIG_MTD_CFI_I1=y
# CONFIG_MTD_CFI_I2 is not set
# CONFIG_MTD_CFI_I4 is not set
# CONFIG_MTD_CFI_I8 is not set
# CONFIG_MTD_OTP is not set
# CONFIG_MTD_CFI_INTELEXT is not set
CONFIG_MTD_CFI_AMDSTD=y
# CONFIG_MTD_CFI_STAA is not set
CONFIG_MTD_CFI_UTIL=y
# CONFIG_MTD_RAM is not set
# CONFIG_MTD_ROM is not set
# CONFIG_MTD_ABSENT is not set
# CONFIG_MTD_XIP is not set
#
# Mapping drivers for chip access
#
# CONFIG_MTD_COMPLEX_MAPPINGS is not set
CONFIG_MTD_PHYSMAP=y
CONFIG_MTD_PHYSMAP_START=0x0
CONFIG_MTD_PHYSMAP_LEN=0x0
CONFIG_MTD_PHYSMAP_BANKWIDTH=2
# CONFIG_MTD_ARM_INTEGRATOR is not set
# CONFIG_MTD_PLATRAM is not set
#
# Self-contained MTD device drivers
#
# CONFIG_MTD_SLRAM is not set
# CONFIG_MTD_PHRAM is not set
# CONFIG_MTD_MTDRAM is not set
# CONFIG_MTD_BLOCK2MTD is not set
#
# Disk-On-Chip Device Drivers
#
# CONFIG_MTD_DOC2000 is not set
# CONFIG_MTD_DOC2001 is not set
# CONFIG_MTD_DOC2001PLUS is not set
# CONFIG_MTD_NAND is not set
# CONFIG_MTD_ONENAND is not set
#
# UBI - Unsorted block images
#
# CONFIG_MTD_UBI is not set
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_MACVLAN is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
CONFIG_MII=y
# CONFIG_AX88796 is not set
CONFIG_SMC91X=y
# CONFIG_DM9000 is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_B44 is not set
# CONFIG_NETDEV_1000 is not set
# CONFIG_NETDEV_10000 is not set
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETCONSOLE is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
# CONFIG_INPUT is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
# CONFIG_VT is not set
CONFIG_DEVKMEM=y
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_TCG_TPM is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
# CONFIG_GPIO_SYSFS is not set
#
# I2C GPIO expanders:
#
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
# CONFIG_SOUND is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_UIO is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4DEV_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_DNOTIFY is not set
CONFIG_INOTIFY=y
CONFIG_INOTIFY_USER=y
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_SYSFS=y
CONFIG_TMPFS=y
# CONFIG_TMPFS_POSIX_ACL is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_ADFS_FS is not set
# CONFIG_AFFS_FS is not set
# CONFIG_HFS_FS is not set
# CONFIG_HFSPLUS_FS is not set
# CONFIG_BEFS_FS is not set
# CONFIG_BFS_FS is not set
# CONFIG_EFS_FS is not set
CONFIG_JFFS2_FS=y
CONFIG_JFFS2_FS_DEBUG=0
CONFIG_JFFS2_FS_WRITEBUFFER=y
# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
# CONFIG_JFFS2_SUMMARY is not set
# CONFIG_JFFS2_FS_XATTR is not set
# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
CONFIG_JFFS2_ZLIB=y
# CONFIG_JFFS2_LZO is not set
CONFIG_JFFS2_RTIME=y
# CONFIG_JFFS2_RUBIN is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
CONFIG_NFS_FS=y
# CONFIG_NFS_V3 is not set
# CONFIG_NFS_V4 is not set
CONFIG_ROOT_NFS=y
# CONFIG_NFSD is not set
CONFIG_LOCKD=y
CONFIG_NFS_COMMON=y
CONFIG_SUNRPC=y
# CONFIG_RPCSEC_GSS_KRB5 is not set
# CONFIG_RPCSEC_GSS_SPKM3 is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
# CONFIG_AFS_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
# CONFIG_DLM is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_DEBUG_BUGVERBOSE is not set
# CONFIG_DEBUG_MEMORY_INIT is not set
CONFIG_FRAME_POINTER=y
# CONFIG_LATENCYTOP is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_HAVE_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
# CONFIG_FTRACE is not set
# CONFIG_IRQSOFF_TRACER is not set
# CONFIG_PREEMPT_TRACER is not set
# CONFIG_SCHED_TRACER is not set
# CONFIG_CONTEXT_SWITCH_TRACER is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_USER is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
# CONFIG_CRYPTO is not set
#
# Library routines
#
CONFIG_BITREVERSE=y
# CONFIG_GENERIC_FIND_FIRST_BIT is not set
# CONFIG_GENERIC_FIND_NEXT_BIT is not set
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
CONFIG_CRC32=y
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_ZLIB_INFLATE=y
CONFIG_ZLIB_DEFLATE=y
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

773
arch/arm/configs/mx31pdk_defconfig 100644
View File

@ -0,0 +1,773 @@
#
# Automatically generated make config: don't edit
# Linux kernel version: 2.6.28-rc2
# Sun Oct 26 15:55:29 2008
#
CONFIG_ARM=y
CONFIG_SYS_SUPPORTS_APM_EMULATION=y
CONFIG_GENERIC_GPIO=y
CONFIG_GENERIC_TIME=y
CONFIG_GENERIC_CLOCKEVENTS=y
CONFIG_MMU=y
# CONFIG_NO_IOPORT is not set
CONFIG_GENERIC_HARDIRQS=y
CONFIG_STACKTRACE_SUPPORT=y
CONFIG_HAVE_LATENCYTOP_SUPPORT=y
CONFIG_LOCKDEP_SUPPORT=y
CONFIG_TRACE_IRQFLAGS_SUPPORT=y
CONFIG_HARDIRQS_SW_RESEND=y
CONFIG_GENERIC_IRQ_PROBE=y
CONFIG_RWSEM_GENERIC_SPINLOCK=y
# CONFIG_ARCH_HAS_ILOG2_U32 is not set
# CONFIG_ARCH_HAS_ILOG2_U64 is not set
CONFIG_GENERIC_HWEIGHT=y
CONFIG_GENERIC_CALIBRATE_DELAY=y
CONFIG_ARCH_MTD_XIP=y
CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
CONFIG_VECTORS_BASE=0xffff0000
CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
#
# General setup
#
# CONFIG_EXPERIMENTAL is not set
CONFIG_BROKEN_ON_SMP=y
CONFIG_INIT_ENV_ARG_LIMIT=32
CONFIG_LOCALVERSION=""
# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
# CONFIG_SYSVIPC is not set
# CONFIG_BSD_PROCESS_ACCT is not set
# CONFIG_TASKSTATS is not set
# CONFIG_AUDIT is not set
# CONFIG_IKCONFIG is not set
CONFIG_LOG_BUF_SHIFT=17
# CONFIG_CGROUPS is not set
# CONFIG_SYSFS_DEPRECATED_V2 is not set
# CONFIG_RELAY is not set
CONFIG_NAMESPACES=y
# CONFIG_UTS_NS is not set
# CONFIG_BLK_DEV_INITRD is not set
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
CONFIG_SYSCTL=y
# CONFIG_EMBEDDED is not set
CONFIG_UID16=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_KALLSYMS=y
# CONFIG_KALLSYMS_EXTRA_PASS is not set
CONFIG_HOTPLUG=y
CONFIG_PRINTK=y
CONFIG_BUG=y
CONFIG_ELF_CORE=y
# CONFIG_COMPAT_BRK is not set
CONFIG_BASE_FULL=y
CONFIG_FUTEX=y
CONFIG_ANON_INODES=y
CONFIG_EPOLL=y
CONFIG_SIGNALFD=y
CONFIG_TIMERFD=y
CONFIG_EVENTFD=y
CONFIG_SHMEM=y
CONFIG_AIO=y
CONFIG_VM_EVENT_COUNTERS=y
CONFIG_SLUB_DEBUG=y
# CONFIG_SLAB is not set
CONFIG_SLUB=y
# CONFIG_SLOB is not set
# CONFIG_PROFILING is not set
# CONFIG_MARKERS is not set
CONFIG_HAVE_OPROFILE=y
CONFIG_HAVE_KPROBES=y
CONFIG_HAVE_KRETPROBES=y
CONFIG_HAVE_GENERIC_DMA_COHERENT=y
CONFIG_SLABINFO=y
CONFIG_RT_MUTEXES=y
# CONFIG_TINY_SHMEM is not set
CONFIG_BASE_SMALL=0
# CONFIG_MODULES is not set
CONFIG_BLOCK=y
# CONFIG_LBD is not set
# CONFIG_BLK_DEV_IO_TRACE is not set
# CONFIG_LSF is not set
# CONFIG_BLK_DEV_INTEGRITY is not set
#
# IO Schedulers
#
CONFIG_IOSCHED_NOOP=y
# CONFIG_IOSCHED_AS is not set
# CONFIG_IOSCHED_DEADLINE is not set
# CONFIG_IOSCHED_CFQ is not set
# CONFIG_DEFAULT_AS is not set
# CONFIG_DEFAULT_DEADLINE is not set
# CONFIG_DEFAULT_CFQ is not set
CONFIG_DEFAULT_NOOP=y
CONFIG_DEFAULT_IOSCHED="noop"
CONFIG_CLASSIC_RCU=y
# CONFIG_FREEZER is not set
#
# System Type
#
# CONFIG_ARCH_AAEC2000 is not set
# CONFIG_ARCH_INTEGRATOR is not set
# CONFIG_ARCH_REALVIEW is not set
# CONFIG_ARCH_VERSATILE is not set
# CONFIG_ARCH_AT91 is not set
# CONFIG_ARCH_CLPS7500 is not set
# CONFIG_ARCH_CLPS711X is not set
# CONFIG_ARCH_EBSA110 is not set
# CONFIG_ARCH_EP93XX is not set
# CONFIG_ARCH_FOOTBRIDGE is not set
# CONFIG_ARCH_NETX is not set
# CONFIG_ARCH_H720X is not set
# CONFIG_ARCH_IMX is not set
# CONFIG_ARCH_IOP13XX is not set
# CONFIG_ARCH_IOP32X is not set
# CONFIG_ARCH_IOP33X is not set
# CONFIG_ARCH_IXP23XX is not set
# CONFIG_ARCH_IXP2000 is not set
# CONFIG_ARCH_IXP4XX is not set
# CONFIG_ARCH_L7200 is not set
# CONFIG_ARCH_KIRKWOOD is not set
# CONFIG_ARCH_KS8695 is not set
# CONFIG_ARCH_NS9XXX is not set
# CONFIG_ARCH_LOKI is not set
# CONFIG_ARCH_MV78XX0 is not set
CONFIG_ARCH_MXC=y
# CONFIG_ARCH_ORION5X is not set
# CONFIG_ARCH_PNX4008 is not set
# CONFIG_ARCH_PXA is not set
# CONFIG_ARCH_RPC is not set
# CONFIG_ARCH_SA1100 is not set
# CONFIG_ARCH_S3C2410 is not set
# CONFIG_ARCH_SHARK is not set
# CONFIG_ARCH_LH7A40X is not set
# CONFIG_ARCH_DAVINCI is not set
# CONFIG_ARCH_OMAP is not set
# CONFIG_ARCH_MSM is not set
#
# Boot options
#
#
# Power management
#
#
# Freescale MXC Implementations
#
# CONFIG_ARCH_MX2 is not set
CONFIG_ARCH_MX3=y
#
# MX3 Options
#
# CONFIG_MACH_MX31ADS is not set
# CONFIG_MACH_PCM037 is not set
# CONFIG_MACH_MX31LITE is not set
CONFIG_MACH_MX31_3DS=y
# CONFIG_MXC_IRQ_PRIOR is not set
#
# Processor Type
#
CONFIG_CPU_32=y
CONFIG_CPU_V6=y
# CONFIG_CPU_32v6K is not set
CONFIG_CPU_32v6=y
CONFIG_CPU_ABRT_EV6=y
CONFIG_CPU_PABRT_NOIFAR=y
CONFIG_CPU_CACHE_V6=y
CONFIG_CPU_CACHE_VIPT=y
CONFIG_CPU_COPY_V6=y
CONFIG_CPU_TLB_V6=y
CONFIG_CPU_HAS_ASID=y
CONFIG_CPU_CP15=y
CONFIG_CPU_CP15_MMU=y
#
# Processor Features
#
CONFIG_ARM_THUMB=y
# CONFIG_CPU_ICACHE_DISABLE is not set
# CONFIG_CPU_DCACHE_DISABLE is not set
# CONFIG_CPU_BPREDICT_DISABLE is not set
# CONFIG_OUTER_CACHE is not set
#
# Bus support
#
# CONFIG_PCI_SYSCALL is not set
# CONFIG_ARCH_SUPPORTS_MSI is not set
# CONFIG_PCCARD is not set
#
# Kernel Features
#
# CONFIG_NO_HZ is not set
# CONFIG_HIGH_RES_TIMERS is not set
CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
CONFIG_VMSPLIT_3G=y
# CONFIG_VMSPLIT_2G is not set
# CONFIG_VMSPLIT_1G is not set
CONFIG_PAGE_OFFSET=0xC0000000
CONFIG_HZ=100
CONFIG_AEABI=y
CONFIG_ARCH_FLATMEM_HAS_HOLES=y
# CONFIG_ARCH_SPARSEMEM_DEFAULT is not set
# CONFIG_ARCH_SELECT_MEMORY_MODEL is not set
CONFIG_FLATMEM=y
CONFIG_FLAT_NODE_MEM_MAP=y
CONFIG_PAGEFLAGS_EXTENDED=y
CONFIG_SPLIT_PTLOCK_CPUS=4
# CONFIG_RESOURCES_64BIT is not set
# CONFIG_PHYS_ADDR_T_64BIT is not set
CONFIG_ZONE_DMA_FLAG=0
CONFIG_VIRT_TO_BUS=y
# CONFIG_UNEVICTABLE_LRU is not set
CONFIG_ALIGNMENT_TRAP=y
#
# Boot options
#
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
CONFIG_CMDLINE=""
# CONFIG_XIP_KERNEL is not set
#
# CPU Power Management
#
# CONFIG_CPU_IDLE is not set
#
# Floating point emulation
#
#
# At least one emulation must be selected
#
# CONFIG_VFP is not set
#
# Userspace binary formats
#
CONFIG_BINFMT_ELF=y
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
CONFIG_HAVE_AOUT=y
# CONFIG_BINFMT_AOUT is not set
# CONFIG_BINFMT_MISC is not set
#
# Power management options
#
# CONFIG_PM is not set
CONFIG_ARCH_SUSPEND_POSSIBLE=y
CONFIG_NET=y
#
# Networking options
#
CONFIG_PACKET=y
# CONFIG_PACKET_MMAP is not set
CONFIG_UNIX=y
CONFIG_XFRM=y
# CONFIG_XFRM_USER is not set
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_IP_MULTICAST is not set
# CONFIG_IP_ADVANCED_ROUTER is not set
CONFIG_IP_FIB_HASH=y
CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
# CONFIG_IP_PNP_BOOTP is not set
# CONFIG_IP_PNP_RARP is not set
# CONFIG_NET_IPIP is not set
# CONFIG_NET_IPGRE is not set
# CONFIG_SYN_COOKIES is not set
# CONFIG_INET_AH is not set
# CONFIG_INET_ESP is not set
# CONFIG_INET_IPCOMP is not set
# CONFIG_INET_XFRM_TUNNEL is not set
CONFIG_INET_TUNNEL=y
CONFIG_INET_XFRM_MODE_TRANSPORT=y
CONFIG_INET_XFRM_MODE_TUNNEL=y
CONFIG_INET_XFRM_MODE_BEET=y
# CONFIG_INET_LRO is not set
CONFIG_INET_DIAG=y
CONFIG_INET_TCP_DIAG=y
# CONFIG_TCP_CONG_ADVANCED is not set
CONFIG_TCP_CONG_CUBIC=y
CONFIG_DEFAULT_TCP_CONG="cubic"
CONFIG_IPV6=y
# CONFIG_IPV6_PRIVACY is not set
# CONFIG_IPV6_ROUTER_PREF is not set
# CONFIG_INET6_AH is not set
# CONFIG_INET6_ESP is not set
# CONFIG_INET6_IPCOMP is not set
# CONFIG_INET6_XFRM_TUNNEL is not set
# CONFIG_INET6_TUNNEL is not set
CONFIG_INET6_XFRM_MODE_TRANSPORT=y
CONFIG_INET6_XFRM_MODE_TUNNEL=y
CONFIG_INET6_XFRM_MODE_BEET=y
CONFIG_IPV6_SIT=y
CONFIG_IPV6_NDISC_NODETYPE=y
# CONFIG_IPV6_TUNNEL is not set
# CONFIG_NETWORK_SECMARK is not set
# CONFIG_NETFILTER is not set
# CONFIG_ATM is not set
# CONFIG_BRIDGE is not set
# CONFIG_VLAN_8021Q is not set
# CONFIG_DECNET is not set
# CONFIG_LLC2 is not set
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
# CONFIG_NET_SCHED is not set
#
# Network testing
#
# CONFIG_NET_PKTGEN is not set
# CONFIG_HAMRADIO is not set
# CONFIG_CAN is not set
# CONFIG_IRDA is not set
# CONFIG_BT is not set
# CONFIG_PHONET is not set
CONFIG_WIRELESS=y
# CONFIG_CFG80211 is not set
CONFIG_WIRELESS_OLD_REGULATORY=y
# CONFIG_WIRELESS_EXT is not set
# CONFIG_MAC80211 is not set
# CONFIG_IEEE80211 is not set
# CONFIG_RFKILL is not set
#
# Device Drivers
#
#
# Generic Driver Options
#
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_STANDALONE=y
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
CONFIG_FW_LOADER=y
# CONFIG_FIRMWARE_IN_KERNEL is not set
CONFIG_EXTRA_FIRMWARE=""
# CONFIG_SYS_HYPERVISOR is not set
# CONFIG_CONNECTOR is not set
# CONFIG_MTD is not set
# CONFIG_PARPORT is not set
# CONFIG_BLK_DEV is not set
# CONFIG_MISC_DEVICES is not set
CONFIG_HAVE_IDE=y
# CONFIG_IDE is not set
#
# SCSI device support
#
# CONFIG_RAID_ATTRS is not set
# CONFIG_SCSI is not set
# CONFIG_SCSI_DMA is not set
# CONFIG_SCSI_NETLINK is not set
# CONFIG_ATA is not set
# CONFIG_MD is not set
CONFIG_NETDEVICES=y
# CONFIG_DUMMY is not set
# CONFIG_BONDING is not set
# CONFIG_EQUALIZER is not set
# CONFIG_TUN is not set
# CONFIG_VETH is not set
# CONFIG_PHYLIB is not set
CONFIG_NET_ETHERNET=y
# CONFIG_MII is not set
# CONFIG_AX88796 is not set
# CONFIG_SMC91X is not set
# CONFIG_DM9000 is not set
# CONFIG_SMC911X is not set
# CONFIG_IBM_NEW_EMAC_ZMII is not set
# CONFIG_IBM_NEW_EMAC_RGMII is not set
# CONFIG_IBM_NEW_EMAC_TAH is not set
# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
# CONFIG_B44 is not set
CONFIG_NETDEV_1000=y
CONFIG_NETDEV_10000=y
#
# Wireless LAN
#
# CONFIG_WLAN_PRE80211 is not set
# CONFIG_WLAN_80211 is not set
# CONFIG_IWLWIFI_LEDS is not set
# CONFIG_WAN is not set
# CONFIG_PPP is not set
# CONFIG_SLIP is not set
# CONFIG_NETPOLL is not set
# CONFIG_NET_POLL_CONTROLLER is not set
# CONFIG_ISDN is not set
#
# Input device support
#
CONFIG_INPUT=y
# CONFIG_INPUT_FF_MEMLESS is not set
# CONFIG_INPUT_POLLDEV is not set
#
# Userland interfaces
#
CONFIG_INPUT_MOUSEDEV=y
# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
# CONFIG_INPUT_JOYDEV is not set
# CONFIG_INPUT_EVDEV is not set
# CONFIG_INPUT_EVBUG is not set
#
# Input Device Drivers
#
# CONFIG_INPUT_KEYBOARD is not set
# CONFIG_INPUT_MOUSE is not set
# CONFIG_INPUT_JOYSTICK is not set
# CONFIG_INPUT_TABLET is not set
# CONFIG_INPUT_TOUCHSCREEN is not set
# CONFIG_INPUT_MISC is not set
#
# Hardware I/O ports
#
# CONFIG_SERIO is not set
# CONFIG_GAMEPORT is not set
#
# Character devices
#
CONFIG_VT=y
CONFIG_CONSOLE_TRANSLATIONS=y
CONFIG_VT_CONSOLE=y
CONFIG_HW_CONSOLE=y
# CONFIG_VT_HW_CONSOLE_BINDING is not set
# CONFIG_DEVKMEM is not set
# CONFIG_SERIAL_NONSTANDARD is not set
#
# Serial drivers
#
# CONFIG_SERIAL_8250 is not set
#
# Non-8250 serial port support
#
CONFIG_SERIAL_IMX=y
CONFIG_SERIAL_IMX_CONSOLE=y
CONFIG_SERIAL_CORE=y
CONFIG_SERIAL_CORE_CONSOLE=y
CONFIG_UNIX98_PTYS=y
# CONFIG_LEGACY_PTYS is not set
# CONFIG_IPMI_HANDLER is not set
# CONFIG_HW_RANDOM is not set
# CONFIG_NVRAM is not set
# CONFIG_R3964 is not set
# CONFIG_RAW_DRIVER is not set
# CONFIG_I2C is not set
# CONFIG_SPI is not set
CONFIG_ARCH_REQUIRE_GPIOLIB=y
CONFIG_GPIOLIB=y
#
# I2C GPIO expanders:
#
#
# PCI GPIO expanders:
#
#
# SPI GPIO expanders:
#
# CONFIG_W1 is not set
# CONFIG_POWER_SUPPLY is not set
# CONFIG_HWMON is not set
# CONFIG_THERMAL is not set
# CONFIG_THERMAL_HWMON is not set
# CONFIG_WATCHDOG is not set
#
# Sonics Silicon Backplane
#
CONFIG_SSB_POSSIBLE=y
# CONFIG_SSB is not set
#
# Multifunction device drivers
#
# CONFIG_MFD_CORE is not set
# CONFIG_MFD_SM501 is not set
# CONFIG_MFD_ASIC3 is not set
# CONFIG_HTC_EGPIO is not set
# CONFIG_HTC_PASIC3 is not set
# CONFIG_MFD_TMIO is not set
# CONFIG_MFD_T7L66XB is not set
# CONFIG_MFD_TC6387XB is not set
# CONFIG_MFD_TC6393XB is not set
# CONFIG_MFD_WM8400 is not set
#
# Multimedia devices
#
#
# Multimedia core support
#
# CONFIG_VIDEO_DEV is not set
# CONFIG_DVB_CORE is not set
# CONFIG_VIDEO_MEDIA is not set
#
# Multimedia drivers
#
# CONFIG_DAB is not set
#
# Graphics support
#
# CONFIG_VGASTATE is not set
# CONFIG_VIDEO_OUTPUT_CONTROL is not set
# CONFIG_FB is not set
# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
#
# Display device support
#
# CONFIG_DISPLAY_SUPPORT is not set
#
# Console display driver support
#
# CONFIG_VGA_CONSOLE is not set
CONFIG_DUMMY_CONSOLE=y
# CONFIG_SOUND is not set
# CONFIG_HID_SUPPORT is not set
# CONFIG_USB_SUPPORT is not set
# CONFIG_MMC is not set
# CONFIG_MEMSTICK is not set
# CONFIG_ACCESSIBILITY is not set
# CONFIG_NEW_LEDS is not set
CONFIG_RTC_LIB=y
# CONFIG_RTC_CLASS is not set
# CONFIG_DMADEVICES is not set
#
# Voltage and Current regulators
#
# CONFIG_REGULATOR is not set
# CONFIG_REGULATOR_FIXED_VOLTAGE is not set
# CONFIG_REGULATOR_VIRTUAL_CONSUMER is not set
# CONFIG_REGULATOR_BQ24022 is not set
# CONFIG_UIO is not set
#
# File systems
#
# CONFIG_EXT2_FS is not set
# CONFIG_EXT3_FS is not set
# CONFIG_EXT4_FS is not set
# CONFIG_REISERFS_FS is not set
# CONFIG_JFS_FS is not set
# CONFIG_FS_POSIX_ACL is not set
CONFIG_FILE_LOCKING=y
# CONFIG_XFS_FS is not set
# CONFIG_OCFS2_FS is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY is not set
# CONFIG_QUOTA is not set
# CONFIG_AUTOFS_FS is not set
# CONFIG_AUTOFS4_FS is not set
# CONFIG_FUSE_FS is not set
#
# CD-ROM/DVD Filesystems
#
# CONFIG_ISO9660_FS is not set
# CONFIG_UDF_FS is not set
#
# DOS/FAT/NT Filesystems
#
# CONFIG_MSDOS_FS is not set
# CONFIG_VFAT_FS is not set
# CONFIG_NTFS_FS is not set
#
# Pseudo filesystems
#
CONFIG_PROC_FS=y
CONFIG_PROC_SYSCTL=y
CONFIG_PROC_PAGE_MONITOR=y
CONFIG_SYSFS=y
# CONFIG_TMPFS is not set
# CONFIG_HUGETLB_PAGE is not set
# CONFIG_CONFIGFS_FS is not set
#
# Miscellaneous filesystems
#
# CONFIG_HFSPLUS_FS is not set
# CONFIG_CRAMFS is not set
# CONFIG_VXFS_FS is not set
# CONFIG_MINIX_FS is not set
# CONFIG_OMFS_FS is not set
# CONFIG_HPFS_FS is not set
# CONFIG_QNX4FS_FS is not set
# CONFIG_ROMFS_FS is not set
# CONFIG_SYSV_FS is not set
# CONFIG_UFS_FS is not set
CONFIG_NETWORK_FILESYSTEMS=y
# CONFIG_NFS_FS is not set
# CONFIG_NFSD is not set
# CONFIG_SMB_FS is not set
# CONFIG_CIFS is not set
# CONFIG_NCP_FS is not set
# CONFIG_CODA_FS is not set
#
# Partition Types
#
# CONFIG_PARTITION_ADVANCED is not set
CONFIG_MSDOS_PARTITION=y
# CONFIG_NLS is not set
#
# Kernel hacking
#
# CONFIG_PRINTK_TIME is not set
# CONFIG_ENABLE_WARN_DEPRECATED is not set
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FRAME_WARN=1024
# CONFIG_MAGIC_SYSRQ is not set
# CONFIG_UNUSED_SYMBOLS is not set
# CONFIG_DEBUG_FS is not set
# CONFIG_HEADERS_CHECK is not set
# CONFIG_DEBUG_KERNEL is not set
# CONFIG_SLUB_DEBUG_ON is not set
# CONFIG_SLUB_STATS is not set
CONFIG_DEBUG_BUGVERBOSE=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_FRAME_POINTER=y
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
# CONFIG_LATENCYTOP is not set
# CONFIG_SYSCTL_SYSCALL_CHECK is not set
CONFIG_NOP_TRACER=y
CONFIG_HAVE_FTRACE=y
CONFIG_HAVE_DYNAMIC_FTRACE=y
# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
# CONFIG_SAMPLES is not set
CONFIG_HAVE_ARCH_KGDB=y
# CONFIG_DEBUG_USER is not set
#
# Security options
#
# CONFIG_KEYS is not set
# CONFIG_SECURITY is not set
# CONFIG_SECURITYFS is not set
# CONFIG_SECURITY_FILE_CAPABILITIES is not set
CONFIG_CRYPTO=y
#
# Crypto core or helper
#
# CONFIG_CRYPTO_FIPS is not set
# CONFIG_CRYPTO_MANAGER is not set
# CONFIG_CRYPTO_NULL is not set
# CONFIG_CRYPTO_CRYPTD is not set
# CONFIG_CRYPTO_AUTHENC is not set
#
# Authenticated Encryption with Associated Data
#
# CONFIG_CRYPTO_CCM is not set
# CONFIG_CRYPTO_GCM is not set
# CONFIG_CRYPTO_SEQIV is not set
#
# Block modes
#
# CONFIG_CRYPTO_CBC is not set
# CONFIG_CRYPTO_CTR is not set
# CONFIG_CRYPTO_CTS is not set
# CONFIG_CRYPTO_ECB is not set
# CONFIG_CRYPTO_PCBC is not set
#
# Hash modes
#
# CONFIG_CRYPTO_HMAC is not set
#
# Digest
#
# CONFIG_CRYPTO_CRC32C is not set
# CONFIG_CRYPTO_MD4 is not set
# CONFIG_CRYPTO_MD5 is not set
# CONFIG_CRYPTO_MICHAEL_MIC is not set
# CONFIG_CRYPTO_RMD128 is not set
# CONFIG_CRYPTO_RMD160 is not set
# CONFIG_CRYPTO_RMD256 is not set
# CONFIG_CRYPTO_RMD320 is not set
# CONFIG_CRYPTO_SHA1 is not set
# CONFIG_CRYPTO_SHA256 is not set
# CONFIG_CRYPTO_SHA512 is not set
# CONFIG_CRYPTO_TGR192 is not set
# CONFIG_CRYPTO_WP512 is not set
#
# Ciphers
#
# CONFIG_CRYPTO_AES is not set
# CONFIG_CRYPTO_ANUBIS is not set
# CONFIG_CRYPTO_ARC4 is not set
# CONFIG_CRYPTO_BLOWFISH is not set
# CONFIG_CRYPTO_CAMELLIA is not set
# CONFIG_CRYPTO_CAST5 is not set
# CONFIG_CRYPTO_CAST6 is not set
# CONFIG_CRYPTO_DES is not set
# CONFIG_CRYPTO_FCRYPT is not set
# CONFIG_CRYPTO_KHAZAD is not set
# CONFIG_CRYPTO_SEED is not set
# CONFIG_CRYPTO_SERPENT is not set
# CONFIG_CRYPTO_TEA is not set
# CONFIG_CRYPTO_TWOFISH is not set
#
# Compression
#
# CONFIG_CRYPTO_DEFLATE is not set
# CONFIG_CRYPTO_LZO is not set
#
# Random Number Generation
#
# CONFIG_CRYPTO_ANSI_CPRNG is not set
CONFIG_CRYPTO_HW=y
#
# Library routines
#
# CONFIG_CRC_CCITT is not set
# CONFIG_CRC16 is not set
# CONFIG_CRC_T10DIF is not set
# CONFIG_CRC_ITU_T is not set
# CONFIG_CRC32 is not set
# CONFIG_CRC7 is not set
# CONFIG_LIBCRC32C is not set
CONFIG_PLIST=y
CONFIG_HAS_IOMEM=y
CONFIG_HAS_IOPORT=y
CONFIG_HAS_DMA=y

14
arch/arm/mach-mx1/Kconfig 100644
View File

@ -0,0 +1,14 @@
if ARCH_MX1
comment "MX1 Platforms"
config MACH_MXLADS
bool
config ARCH_MX1ADS
bool "MX1ADS platform"
select MACH_MXLADS
help
Say Y here if you are using Motorola MX1ADS/MXLADS boards
endif

10
arch/arm/mach-mx1/Makefile 100644
View File

@ -0,0 +1,10 @@
#
# Makefile for the linux kernel.
#
# Object file lists.
obj-y += generic.o clock.o devices.o
# Specific board support
obj-$(CONFIG_ARCH_MX1ADS) += mx1ads.o

4
arch/arm/mach-mx1/Makefile.boot 100644
View File

@ -0,0 +1,4 @@
zreladdr-y := 0x08008000
params_phys-y := 0x08000100
initrd_phys-y := 0x08800000

656
arch/arm/mach-mx1/clock.c 100644
View File

@ -0,0 +1,656 @@
/*
* Copyright (C) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/math64.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <mach/clock.h>
#include <mach/hardware.h>
#include "crm_regs.h"
static int _clk_enable(struct clk *clk)
{
unsigned int reg;
reg = __raw_readl(clk->enable_reg);
reg |= 1 << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
return 0;
}
static void _clk_disable(struct clk *clk)
{
unsigned int reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(1 << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
}
static int _clk_can_use_parent(const struct clk *clk_arr[], unsigned int size,
struct clk *parent)
{
int i;
for (i = 0; i < size; i++)
if (parent == clk_arr[i])
return i;
return -EINVAL;
}
static unsigned long
_clk_simple_round_rate(struct clk *clk, unsigned long rate, unsigned int limit)
{
int div;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (parent_rate % rate)
div++;
if (div > limit)
div = limit;
return parent_rate / div;
}
static unsigned long _clk_parent_round_rate(struct clk *clk, unsigned long rate)
{
return clk->parent->round_rate(clk->parent, rate);
}
static int _clk_parent_set_rate(struct clk *clk, unsigned long rate)
{
return clk->parent->set_rate(clk->parent, rate);
}
/*
* get the system pll clock in Hz
*
* mfi + mfn / (mfd +1)
* f = 2 * f_ref * --------------------
* pd + 1
*/
static unsigned long mx1_decode_pll(unsigned int pll, u32 f_ref)
{
unsigned long long ll;
unsigned long quot;
u32 mfi = (pll >> 10) & 0xf;
u32 mfn = pll & 0x3ff;
u32 mfd = (pll >> 16) & 0x3ff;
u32 pd = (pll >> 26) & 0xf;
mfi = mfi <= 5 ? 5 : mfi;
ll = 2 * (unsigned long long)f_ref *
((mfi << 16) + (mfn << 16) / (mfd + 1));
quot = (pd + 1) * (1 << 16);
ll += quot / 2;
do_div(ll, quot);
return (unsigned long)ll;
}
static unsigned long clk16m_get_rate(struct clk *clk)
{
return 16000000;
}
static struct clk clk16m = {
.name = "CLK16M",
.get_rate = clk16m_get_rate,
.enable = _clk_enable,
.enable_reg = CCM_CSCR,
.enable_shift = CCM_CSCR_OSC_EN_SHIFT,
.disable = _clk_disable,
};
/* in Hz */
static unsigned long clk32_rate;
static unsigned long clk32_get_rate(struct clk *clk)
{
return clk32_rate;
}
static struct clk clk32 = {
.name = "CLK32",
.get_rate = clk32_get_rate,
};
static unsigned long clk32_premult_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) * 512;
}
static struct clk clk32_premult = {
.name = "CLK32_premultiplier",
.parent = &clk32,
.get_rate = clk32_premult_get_rate,
};
static const struct clk *prem_clk_clocks[] = {
&clk32_premult,
&clk16m,
};
static int prem_clk_set_parent(struct clk *clk, struct clk *parent)
{
int i;
unsigned int reg = __raw_readl(CCM_CSCR);
i = _clk_can_use_parent(prem_clk_clocks, ARRAY_SIZE(prem_clk_clocks),
parent);
switch (i) {
case 0:
reg &= ~CCM_CSCR_SYSTEM_SEL;
break;
case 1:
reg |= CCM_CSCR_SYSTEM_SEL;
break;
default:
return i;
}
__raw_writel(reg, CCM_CSCR);
return 0;
}
static struct clk prem_clk = {
.name = "prem_clk",
.set_parent = prem_clk_set_parent,
};
static unsigned long system_clk_get_rate(struct clk *clk)
{
return mx1_decode_pll(__raw_readl(CCM_SPCTL0),
clk_get_rate(clk->parent));
}
static struct clk system_clk = {
.name = "system_clk",
.parent = &prem_clk,
.get_rate = system_clk_get_rate,
};
static unsigned long mcu_clk_get_rate(struct clk *clk)
{
return mx1_decode_pll(__raw_readl(CCM_MPCTL0),
clk_get_rate(clk->parent));
}
static struct clk mcu_clk = {
.name = "mcu_clk",
.parent = &clk32_premult,
.get_rate = mcu_clk_get_rate,
};
static unsigned long fclk_get_rate(struct clk *clk)
{
unsigned long fclk = clk_get_rate(clk->parent);
if (__raw_readl(CCM_CSCR) & CCM_CSCR_PRESC)
fclk /= 2;
return fclk;
}
static struct clk fclk = {
.name = "fclk",
.parent = &mcu_clk,
.get_rate = fclk_get_rate,
};
/*
* get hclk ( SDRAM, CSI, Memory Stick, I2C, DMA )
*/
static unsigned long hclk_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
CCM_CSCR_BCLK_MASK) >> CCM_CSCR_BCLK_OFFSET) + 1);
}
static unsigned long hclk_round_rate(struct clk *clk, unsigned long rate)
{
return _clk_simple_round_rate(clk, rate, 16);
}
static int hclk_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int div;
unsigned int reg;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 16 || div < 1 || ((parent_rate / div) != rate))
return -EINVAL;
div--;
reg = __raw_readl(CCM_CSCR);
reg &= ~CCM_CSCR_BCLK_MASK;
reg |= div << CCM_CSCR_BCLK_OFFSET;
__raw_writel(reg, CCM_CSCR);
return 0;
}
static struct clk hclk = {
.name = "hclk",
.parent = &system_clk,
.get_rate = hclk_get_rate,
.round_rate = hclk_round_rate,
.set_rate = hclk_set_rate,
};
static unsigned long clk48m_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / (((__raw_readl(CCM_CSCR) &
CCM_CSCR_USB_MASK) >> CCM_CSCR_USB_OFFSET) + 1);
}
static unsigned long clk48m_round_rate(struct clk *clk, unsigned long rate)
{
return _clk_simple_round_rate(clk, rate, 8);
}
static int clk48m_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int div;
unsigned int reg;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 8 || div < 1 || ((parent_rate / div) != rate))
return -EINVAL;
div--;
reg = __raw_readl(CCM_CSCR);
reg &= ~CCM_CSCR_USB_MASK;
reg |= div << CCM_CSCR_USB_OFFSET;
__raw_writel(reg, CCM_CSCR);
return 0;
}
static struct clk clk48m = {
.name = "CLK48M",
.parent = &system_clk,
.get_rate = clk48m_get_rate,
.round_rate = clk48m_round_rate,
.set_rate = clk48m_set_rate,
};
/*
* get peripheral clock 1 ( UART[12], Timer[12], PWM )
*/
static unsigned long perclk1_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
CCM_PCDR_PCLK1_MASK) >> CCM_PCDR_PCLK1_OFFSET) + 1);
}
static unsigned long perclk1_round_rate(struct clk *clk, unsigned long rate)
{
return _clk_simple_round_rate(clk, rate, 16);
}
static int perclk1_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int div;
unsigned int reg;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 16 || div < 1 || ((parent_rate / div) != rate))
return -EINVAL;
div--;
reg = __raw_readl(CCM_PCDR);
reg &= ~CCM_PCDR_PCLK1_MASK;
reg |= div << CCM_PCDR_PCLK1_OFFSET;
__raw_writel(reg, CCM_PCDR);
return 0;
}
/*
* get peripheral clock 2 ( LCD, SD, SPI[12] )
*/
static unsigned long perclk2_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
CCM_PCDR_PCLK2_MASK) >> CCM_PCDR_PCLK2_OFFSET) + 1);
}
static unsigned long perclk2_round_rate(struct clk *clk, unsigned long rate)
{
return _clk_simple_round_rate(clk, rate, 16);
}
static int perclk2_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int div;
unsigned int reg;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 16 || div < 1 || ((parent_rate / div) != rate))
return -EINVAL;
div--;
reg = __raw_readl(CCM_PCDR);
reg &= ~CCM_PCDR_PCLK2_MASK;
reg |= div << CCM_PCDR_PCLK2_OFFSET;
__raw_writel(reg, CCM_PCDR);
return 0;
}
/*
* get peripheral clock 3 ( SSI )
*/
static unsigned long perclk3_get_rate(struct clk *clk)
{
return clk_get_rate(clk->parent) / (((__raw_readl(CCM_PCDR) &
CCM_PCDR_PCLK3_MASK) >> CCM_PCDR_PCLK3_OFFSET) + 1);
}
static unsigned long perclk3_round_rate(struct clk *clk, unsigned long rate)
{
return _clk_simple_round_rate(clk, rate, 128);
}
static int perclk3_set_rate(struct clk *clk, unsigned long rate)
{
unsigned int div;
unsigned int reg;
unsigned long parent_rate;
parent_rate = clk_get_rate(clk->parent);
div = parent_rate / rate;
if (div > 128 || div < 1 || ((parent_rate / div) != rate))
return -EINVAL;
div--;
reg = __raw_readl(CCM_PCDR);
reg &= ~CCM_PCDR_PCLK3_MASK;
reg |= div << CCM_PCDR_PCLK3_OFFSET;
__raw_writel(reg, CCM_PCDR);
return 0;
}
static struct clk perclk[] = {
{
.name = "perclk",
.id = 0,
.parent = &system_clk,
.get_rate = perclk1_get_rate,
.round_rate = perclk1_round_rate,
.set_rate = perclk1_set_rate,
}, {
.name = "perclk",
.id = 1,
.parent = &system_clk,
.get_rate = perclk2_get_rate,
.round_rate = perclk2_round_rate,
.set_rate = perclk2_set_rate,
}, {
.name = "perclk",
.id = 2,
.parent = &system_clk,
.get_rate = perclk3_get_rate,
.round_rate = perclk3_round_rate,
.set_rate = perclk3_set_rate,
}
};
static const struct clk *clko_clocks[] = {
&perclk[0],
&hclk,
&clk48m,
&clk16m,
&prem_clk,
&fclk,
};
static int clko_set_parent(struct clk *clk, struct clk *parent)
{
int i;
unsigned int reg;
i = _clk_can_use_parent(clko_clocks, ARRAY_SIZE(clko_clocks), parent);
if (i < 0)
return i;
reg = __raw_readl(CCM_CSCR) & ~CCM_CSCR_CLKO_MASK;
reg |= i << CCM_CSCR_CLKO_OFFSET;
__raw_writel(reg, CCM_CSCR);
if (clko_clocks[i]->set_rate && clko_clocks[i]->round_rate) {
clk->set_rate = _clk_parent_set_rate;
clk->round_rate = _clk_parent_round_rate;
} else {
clk->set_rate = NULL;
clk->round_rate = NULL;
}
return 0;
}
static struct clk clko_clk = {
.name = "clko_clk",
.set_parent = clko_set_parent,
};
static struct clk dma_clk = {
.name = "dma_clk",
.parent = &hclk,
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
.enable = _clk_enable,
.enable_reg = SCM_GCCR,
.enable_shift = SCM_GCCR_DMA_CLK_EN_OFFSET,
.disable = _clk_disable,
};
static struct clk csi_clk = {
.name = "csi_clk",
.parent = &hclk,
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
.enable = _clk_enable,
.enable_reg = SCM_GCCR,
.enable_shift = SCM_GCCR_CSI_CLK_EN_OFFSET,
.disable = _clk_disable,
};
static struct clk mma_clk = {
.name = "mma_clk",
.parent = &hclk,
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
.enable = _clk_enable,
.enable_reg = SCM_GCCR,
.enable_shift = SCM_GCCR_MMA_CLK_EN_OFFSET,
.disable = _clk_disable,
};
static struct clk usbd_clk = {
.name = "usbd_clk",
.parent = &clk48m,
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
.enable = _clk_enable,
.enable_reg = SCM_GCCR,
.enable_shift = SCM_GCCR_USBD_CLK_EN_OFFSET,
.disable = _clk_disable,
};
static struct clk gpt_clk = {
.name = "gpt_clk",
.parent = &perclk[0],
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk uart_clk = {
.name = "uart_clk",
.parent = &perclk[0],
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk i2c_clk = {
.name = "i2c_clk",
.parent = &hclk,
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk spi_clk = {
.name = "spi_clk",
.parent = &perclk[1],
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk sdhc_clk = {
.name = "sdhc_clk",
.parent = &perclk[1],
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk lcdc_clk = {
.name = "lcdc_clk",
.parent = &perclk[1],
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk mshc_clk = {
.name = "mshc_clk",
.parent = &hclk,
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk ssi_clk = {
.name = "ssi_clk",
.parent = &perclk[2],
.round_rate = _clk_parent_round_rate,
.set_rate = _clk_parent_set_rate,
};
static struct clk rtc_clk = {
.name = "rtc_clk",
.parent = &clk32,
};
static struct clk *mxc_clks[] = {
&clk16m,
&clk32,
&clk32_premult,
&prem_clk,
&system_clk,
&mcu_clk,
&fclk,
&hclk,
&clk48m,
&perclk[0],
&perclk[1],
&perclk[2],
&clko_clk,
&dma_clk,
&csi_clk,
&mma_clk,
&usbd_clk,
&gpt_clk,
&uart_clk,
&i2c_clk,
&spi_clk,
&sdhc_clk,
&lcdc_clk,
&mshc_clk,
&ssi_clk,
&rtc_clk,
};
int __init mxc_clocks_init(unsigned long fref)
{
struct clk **clkp;
unsigned int reg;
/* disable clocks we are able to */
__raw_writel(0, SCM_GCCR);
clk32_rate = fref;
reg = __raw_readl(CCM_CSCR);
/* detect clock reference for system PLL */
if (reg & CCM_CSCR_SYSTEM_SEL) {
prem_clk.parent = &clk16m;
} else {
/* ensure that oscillator is disabled */
reg &= ~(1 << CCM_CSCR_OSC_EN_SHIFT);
__raw_writel(reg, CCM_CSCR);
prem_clk.parent = &clk32_premult;
}
/* detect reference for CLKO */
reg = (reg & CCM_CSCR_CLKO_MASK) >> CCM_CSCR_CLKO_OFFSET;
clko_clk.parent = (struct clk *)clko_clocks[reg];
for (clkp = mxc_clks; clkp < mxc_clks + ARRAY_SIZE(mxc_clks); clkp++)
clk_register(*clkp);
clk_enable(&hclk);
clk_enable(&fclk);
return 0;
}

55
arch/arm/mach-mx1/crm_regs.h 100644
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/*
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This file may be distributed under the terms of the GNU General
* Public License, version 2.
*/
#ifndef __ARCH_ARM_MACH_MX1_CRM_REGS_H__
#define __ARCH_ARM_MACH_MX1_CRM_REGS_H__
#define CCM_BASE IO_ADDRESS(CCM_BASE_ADDR)
#define SCM_BASE IO_ADDRESS(SCM_BASE_ADDR)
/* CCM register addresses */
#define CCM_CSCR (CCM_BASE + 0x0)
#define CCM_MPCTL0 (CCM_BASE + 0x4)
#define CCM_MPCTL1 (CCM_BASE + 0x8)
#define CCM_SPCTL0 (CCM_BASE + 0xC)
#define CCM_SPCTL1 (CCM_BASE + 0x10)
#define CCM_PCDR (CCM_BASE + 0x20)
#define CCM_CSCR_CLKO_OFFSET 29
#define CCM_CSCR_CLKO_MASK (0x7 << 29)
#define CCM_CSCR_USB_OFFSET 26
#define CCM_CSCR_USB_MASK (0x7 << 26)
#define CCM_CSCR_SPLL_RESTART (1 << 22)
#define CCM_CSCR_MPLL_RESTART (1 << 21)
#define CCM_CSCR_OSC_EN_SHIFT 17
#define CCM_CSCR_SYSTEM_SEL (1 << 16)
#define CCM_CSCR_BCLK_OFFSET 10
#define CCM_CSCR_BCLK_MASK (0xF << 10)
#define CCM_CSCR_PRESC (1 << 15)
#define CCM_CSCR_SPEN (1 << 1)
#define CCM_CSCR_MPEN (1 << 0)
#define CCM_PCDR_PCLK3_OFFSET 16
#define CCM_PCDR_PCLK3_MASK (0x7F << 16)
#define CCM_PCDR_PCLK2_OFFSET 4
#define CCM_PCDR_PCLK2_MASK (0xF << 4)
#define CCM_PCDR_PCLK1_OFFSET 0
#define CCM_PCDR_PCLK1_MASK 0xF
/* SCM register addresses */
#define SCM_SIDR (SCM_BASE + 0x0)
#define SCM_FMCR (SCM_BASE + 0x4)
#define SCM_GPCR (SCM_BASE + 0x8)
#define SCM_GCCR (SCM_BASE + 0xC)
#define SCM_GCCR_DMA_CLK_EN_OFFSET 3
#define SCM_GCCR_CSI_CLK_EN_OFFSET 2
#define SCM_GCCR_MMA_CLK_EN_OFFSET 1
#define SCM_GCCR_USBD_CLK_EN_OFFSET 0
#endif /* __ARCH_ARM_MACH_MX2_CRM_REGS_H__ */

260
arch/arm/mach-mx1/devices.c 100644
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/*
* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright 2008 Sascha Hauer, kernel@pengutronix.de
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
* Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor,
* Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <mach/hardware.h>
static struct resource imx_csi_resources[] = {
[0] = {
.start = 0x00224000,
.end = 0x00224010,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = CSI_INT,
.end = CSI_INT,
.flags = IORESOURCE_IRQ,
},
};
static u64 imx_csi_dmamask = 0xffffffffUL;
struct platform_device imx_csi_device = {
.name = "imx-csi",
.id = 0, /* This is used to put cameras on this interface */
.dev = {
.dma_mask = &imx_csi_dmamask,
.coherent_dma_mask = 0xffffffff,
},
.resource = imx_csi_resources,
.num_resources = ARRAY_SIZE(imx_csi_resources),
};
static struct resource imx_i2c_resources[] = {
[0] = {
.start = 0x00217000,
.end = 0x00217010,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = I2C_INT,
.end = I2C_INT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_i2c_device = {
.name = "imx-i2c",
.id = 0,
.resource = imx_i2c_resources,
.num_resources = ARRAY_SIZE(imx_i2c_resources),
};
static struct resource imx_uart1_resources[] = {
[0] = {
.start = UART1_BASE_ADDR,
.end = UART1_BASE_ADDR + 0xD0,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = UART1_MINT_RX,
.end = UART1_MINT_RX,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = UART1_MINT_TX,
.end = UART1_MINT_TX,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = UART1_MINT_RTS,
.end = UART1_MINT_RTS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_uart1_device = {
.name = "imx-uart",
.id = 0,
.num_resources = ARRAY_SIZE(imx_uart1_resources),
.resource = imx_uart1_resources,
};
static struct resource imx_uart2_resources[] = {
[0] = {
.start = UART2_BASE_ADDR,
.end = UART2_BASE_ADDR + 0xD0,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = UART2_MINT_RX,
.end = UART2_MINT_RX,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = UART2_MINT_TX,
.end = UART2_MINT_TX,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = UART2_MINT_RTS,
.end = UART2_MINT_RTS,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_uart2_device = {
.name = "imx-uart",
.id = 1,
.num_resources = ARRAY_SIZE(imx_uart2_resources),
.resource = imx_uart2_resources,
};
static struct resource imx_rtc_resources[] = {
[0] = {
.start = 0x00204000,
.end = 0x00204024,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = RTC_INT,
.end = RTC_INT,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = RTC_SAMINT,
.end = RTC_SAMINT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_rtc_device = {
.name = "rtc-imx",
.id = 0,
.resource = imx_rtc_resources,
.num_resources = ARRAY_SIZE(imx_rtc_resources),
};
static struct resource imx_wdt_resources[] = {
[0] = {
.start = 0x00201000,
.end = 0x00201008,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = WDT_INT,
.end = WDT_INT,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_wdt_device = {
.name = "imx-wdt",
.id = 0,
.resource = imx_wdt_resources,
.num_resources = ARRAY_SIZE(imx_wdt_resources),
};
static struct resource imx_usb_resources[] = {
[0] = {
.start = 0x00212000,
.end = 0x00212148,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = USBD_INT0,
.end = USBD_INT0,
.flags = IORESOURCE_IRQ,
},
[2] = {
.start = USBD_INT1,
.end = USBD_INT1,
.flags = IORESOURCE_IRQ,
},
[3] = {
.start = USBD_INT2,
.end = USBD_INT2,
.flags = IORESOURCE_IRQ,
},
[4] = {
.start = USBD_INT3,
.end = USBD_INT3,
.flags = IORESOURCE_IRQ,
},
[5] = {
.start = USBD_INT4,
.end = USBD_INT4,
.flags = IORESOURCE_IRQ,
},
[6] = {
.start = USBD_INT5,
.end = USBD_INT5,
.flags = IORESOURCE_IRQ,
},
[7] = {
.start = USBD_INT6,
.end = USBD_INT6,
.flags = IORESOURCE_IRQ,
},
};
struct platform_device imx_usb_device = {
.name = "imx_udc",
.id = 0,
.num_resources = ARRAY_SIZE(imx_usb_resources),
.resource = imx_usb_resources,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
[0] = {
.chip.label = "gpio-0",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR),
.irq = GPIO_INT_PORTA,
.virtual_irq_start = MXC_MAX_INT_LINES
},
[1] = {
.chip.label = "gpio-1",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x100),
.irq = GPIO_INT_PORTB,
.virtual_irq_start = MXC_MAX_INT_LINES + 32
},
[2] = {
.chip.label = "gpio-2",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x200),
.irq = GPIO_INT_PORTC,
.virtual_irq_start = MXC_MAX_INT_LINES + 64
},
[3] = {
.chip.label = "gpio-3",
.base = (void __iomem *)IO_ADDRESS(GPIO_BASE_ADDR + 0x300),
.irq = GPIO_INT_PORTD,
.virtual_irq_start = MXC_MAX_INT_LINES + 96
}
};
int __init mxc_register_gpios(void)
{
return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
}

7
arch/arm/mach-mx1/devices.h 100644
View File

@ -0,0 +1,7 @@
extern struct platform_device imx_csi_device;
extern struct platform_device imx_i2c_device;
extern struct platform_device imx_uart1_device;
extern struct platform_device imx_uart2_device;
extern struct platform_device imx_rtc_device;
extern struct platform_device imx_wdt_device;
extern struct platform_device imx_usb_device;

43
arch/arm/mach-mx1/generic.c 100644
View File

@ -0,0 +1,43 @@
/*
* author: Sascha Hauer
* Created: april 20th, 2004
* Copyright: Synertronixx GmbH
*
* Common code for i.MX machines
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
#include <asm/mach/map.h>
#include <mach/hardware.h>
static struct map_desc imx_io_desc[] __initdata = {
{
.virtual = IMX_IO_BASE,
.pfn = __phys_to_pfn(IMX_IO_PHYS),
.length = IMX_IO_SIZE,
.type = MT_DEVICE
}
};
void __init mxc_map_io(void)
{
iotable_init(imx_io_desc, ARRAY_SIZE(imx_io_desc));
}

148
arch/arm/mach-mx1/mx1ads.c 100644
View File

@ -0,0 +1,148 @@
/*
* arch/arm/mach-imx/mx1ads.c
*
* Initially based on:
* linux-2.6.7-imx/arch/arm/mach-imx/scb9328.c
* Copyright (c) 2004 Sascha Hauer <sascha@saschahauer.de>
*
* 2004 (c) MontaVista Software, Inc.
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <mach/hardware.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx1-mx2.h>
#include "devices.h"
/*
* UARTs platform data
*/
static int mxc_uart1_pins[] = {
PC9_PF_UART1_CTS,
PC10_PF_UART1_RTS,
PC11_PF_UART1_TXD,
PC12_PF_UART1_RXD,
};
static int uart1_mxc_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins), "UART1");
}
static int uart1_mxc_exit(struct platform_device *pdev)
{
mxc_gpio_release_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins));
return 0;
}
static int mxc_uart2_pins[] = {
PB28_PF_UART2_CTS,
PB29_PF_UART2_RTS,
PB30_PF_UART2_TXD,
PB31_PF_UART2_RXD,
};
static int uart2_mxc_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins), "UART2");
}
static int uart2_mxc_exit(struct platform_device *pdev)
{
mxc_gpio_release_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins));
return 0;
}
static struct imxuart_platform_data uart_pdata[] = {
{
.init = uart1_mxc_init,
.exit = uart1_mxc_exit,
.flags = IMXUART_HAVE_RTSCTS,
}, {
.init = uart2_mxc_init,
.exit = uart2_mxc_exit,
.flags = IMXUART_HAVE_RTSCTS,
},
};
/*
* Physmap flash
*/
static struct physmap_flash_data mx1ads_flash_data = {
.width = 4, /* bankwidth in bytes */
};
static struct resource flash_resource = {
.start = IMX_CS0_PHYS,
.end = IMX_CS0_PHYS + SZ_32M - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device flash_device = {
.name = "physmap-flash",
.id = 0,
.resource = &flash_resource,
.num_resources = 1,
};
/*
* Board init
*/
static void __init mx1ads_init(void)
{
/* UART */
mxc_register_device(&imx_uart1_device, &uart_pdata[0]);
mxc_register_device(&imx_uart2_device, &uart_pdata[1]);
/* Physmap flash */
mxc_register_device(&flash_device, &mx1ads_flash_data);
}
static void __init mx1ads_timer_init(void)
{
mxc_clocks_init(32000);
mxc_timer_init("gpt_clk");
}
struct sys_timer mx1ads_timer = {
.init = mx1ads_timer_init,
};
MACHINE_START(MX1ADS, "Freescale MX1ADS")
/* Maintainer: Sascha Hauer, Pengutronix */
.phys_io = IMX_IO_PHYS,
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mxc_map_io,
.init_irq = mxc_init_irq,
.timer = &mx1ads_timer,
.init_machine = mx1ads_init,
MACHINE_END
MACHINE_START(MXLADS, "Freescale MXLADS")
.phys_io = IMX_IO_PHYS,
.io_pg_offst = (IMX_IO_BASE >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mxc_map_io,
.init_irq = mxc_init_irq,
.timer = &mx1ads_timer,
.init_machine = mx1ads_init,
MACHINE_END

19
arch/arm/mach-mx2/devices.c
View File

@ -205,6 +205,25 @@ struct platform_device mxc_w1_master_device = {
.resource = mxc_w1_master_resources,
};
static struct resource mxc_nand_resources[] = {
{
.start = NFC_BASE_ADDR,
.end = NFC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM
}, {
.start = MXC_INT_NANDFC,
.end = MXC_INT_NANDFC,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mxc_nand_device = {
.name = "mxc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_nand_resources),
.resource = mxc_nand_resources,
};
/* GPIO port description */
static struct mxc_gpio_port imx_gpio_ports[] = {
[0] = {

1
arch/arm/mach-mx2/devices.h
View File

@ -13,3 +13,4 @@ extern struct platform_device mxc_uart_device3;
extern struct platform_device mxc_uart_device4;
extern struct platform_device mxc_uart_device5;
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_nand_device;

61
arch/arm/mach-mx2/mx27ads.c
View File

@ -68,15 +68,14 @@ static int mxc_uart0_pins[] = {
static int uart_mxc_port0_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
ARRAY_SIZE(mxc_uart0_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
ARRAY_SIZE(mxc_uart0_pins), "UART0");
}
static int uart_mxc_port0_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
ARRAY_SIZE(mxc_uart0_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
mxc_gpio_release_multiple_pins(mxc_uart0_pins,
ARRAY_SIZE(mxc_uart0_pins));
return 0;
}
static int mxc_uart1_pins[] = {
@ -89,15 +88,14 @@ static int mxc_uart1_pins[] = {
static int uart_mxc_port1_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
ARRAY_SIZE(mxc_uart1_pins), "UART1");
}
static int uart_mxc_port1_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
mxc_gpio_setup_release_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins));
return 0;
}
static int mxc_uart2_pins[] = {
@ -110,15 +108,14 @@ static int mxc_uart2_pins[] = {
static int uart_mxc_port2_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
ARRAY_SIZE(mxc_uart2_pins), "UART2");
}
static int uart_mxc_port2_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
mxc_gpio_release_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins));
return 0;
}
static int mxc_uart3_pins[] = {
@ -131,15 +128,13 @@ static int mxc_uart3_pins[] = {
static int uart_mxc_port3_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
ARRAY_SIZE(mxc_uart3_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART3");
ARRAY_SIZE(mxc_uart3_pins), "UART3");
}
static int uart_mxc_port3_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart3_pins,
ARRAY_SIZE(mxc_uart3_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART3");
mxc_gpio_release_multiple_pins(mxc_uart3_pins,
ARRAY_SIZE(mxc_uart3_pins));
}
static int mxc_uart4_pins[] = {
@ -152,15 +147,14 @@ static int mxc_uart4_pins[] = {
static int uart_mxc_port4_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
ARRAY_SIZE(mxc_uart4_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART4");
ARRAY_SIZE(mxc_uart4_pins), "UART4");
}
static int uart_mxc_port4_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart4_pins,
ARRAY_SIZE(mxc_uart4_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART4");
mxc_gpio_release_multiple_pins(mxc_uart4_pins,
ARRAY_SIZE(mxc_uart4_pins));
return 0;
}
static int mxc_uart5_pins[] = {
@ -173,15 +167,14 @@ static int mxc_uart5_pins[] = {
static int uart_mxc_port5_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
ARRAY_SIZE(mxc_uart5_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART5");
ARRAY_SIZE(mxc_uart5_pins), "UART5");
}
static int uart_mxc_port5_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart5_pins,
ARRAY_SIZE(mxc_uart5_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART5");
mxc_gpio_release_multiple_pins(mxc_uart5_pins,
ARRAY_SIZE(mxc_uart5_pins));
return 0;
}
static struct platform_device *platform_devices[] __initdata = {
@ -212,15 +205,13 @@ static int mxc_fec_pins[] = {
static void gpio_fec_active(void)
{
mxc_gpio_setup_multiple_pins(mxc_fec_pins,
ARRAY_SIZE(mxc_fec_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
ARRAY_SIZE(mxc_fec_pins), "FEC");
}
static void gpio_fec_inactive(void)
{
mxc_gpio_setup_multiple_pins(mxc_fec_pins,
ARRAY_SIZE(mxc_fec_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
mxc_gpio_release_multiple_pins(mxc_fec_pins,
ARRAY_SIZE(mxc_fec_pins));
}
static struct imxuart_platform_data uart_pdata[] = {

80
arch/arm/mach-mx2/pcm038.c
View File

@ -19,6 +19,7 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include <mach/common.h>
@ -27,9 +28,35 @@
#include <asm/mach/time.h>
#include <mach/imx-uart.h>
#include <mach/board-pcm038.h>
#include <mach/mxc_nand.h>
#include "devices.h"
/*
* Phytec's PCM038 comes with 2MiB battery buffered SRAM,
* 16 bit width
*/
static struct platdata_mtd_ram pcm038_sram_data = {
.bankwidth = 2,
};
static struct resource pcm038_sram_resource = {
.start = CS1_BASE_ADDR,
.end = CS1_BASE_ADDR + 512 * 1024 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device pcm038_sram_mtd_device = {
.name = "mtd-ram",
.id = 0,
.dev = {
.platform_data = &pcm038_sram_data,
},
.num_resources = 1,
.resource = &pcm038_sram_resource,
};
/*
* Phytec's phyCORE-i.MX27 comes with 32MiB flash,
* 16 bit width
@ -64,15 +91,14 @@ static int mxc_uart0_pins[] = {
static int uart_mxc_port0_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
ARRAY_SIZE(mxc_uart0_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART0");
ARRAY_SIZE(mxc_uart0_pins), "UART0");
}
static int uart_mxc_port0_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
ARRAY_SIZE(mxc_uart0_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART0");
mxc_gpio_release_multiple_pins(mxc_uart0_pins,
ARRAY_SIZE(mxc_uart0_pins));
return 0;
}
static int mxc_uart1_pins[] = {
@ -85,15 +111,14 @@ static int mxc_uart1_pins[] = {
static int uart_mxc_port1_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART1");
ARRAY_SIZE(mxc_uart1_pins), "UART1");
}
static int uart_mxc_port1_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART1");
mxc_gpio_release_multiple_pins(mxc_uart1_pins,
ARRAY_SIZE(mxc_uart1_pins));
return 0;
}
static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
@ -104,15 +129,14 @@ static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
static int uart_mxc_port2_init(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "UART2");
ARRAY_SIZE(mxc_uart2_pins), "UART2");
}
static int uart_mxc_port2_exit(struct platform_device *pdev)
{
return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "UART2");
mxc_gpio_release_multiple_pins(mxc_uart2_pins,
ARRAY_SIZE(mxc_uart2_pins));
return 0;
}
static struct imxuart_platform_data uart_pdata[] = {
@ -155,30 +179,46 @@ static int mxc_fec_pins[] = {
static void gpio_fec_active(void)
{
mxc_gpio_setup_multiple_pins(mxc_fec_pins,
ARRAY_SIZE(mxc_fec_pins),
MXC_GPIO_ALLOC_MODE_NORMAL, "FEC");
ARRAY_SIZE(mxc_fec_pins), "FEC");
}
static void gpio_fec_inactive(void)
{
mxc_gpio_setup_multiple_pins(mxc_fec_pins,
ARRAY_SIZE(mxc_fec_pins),
MXC_GPIO_ALLOC_MODE_RELEASE, "FEC");
mxc_gpio_release_multiple_pins(mxc_fec_pins,
ARRAY_SIZE(mxc_fec_pins));
}
static struct mxc_nand_platform_data pcm038_nand_board_info = {
.width = 1,
.hw_ecc = 1,
};
static struct platform_device *platform_devices[] __initdata = {
&pcm038_nor_mtd_device,
&mxc_w1_master_device,
&pcm038_sram_mtd_device,
};
/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
* setup other stuffs to access the sram. */
static void __init pcm038_init_sram(void)
{
__raw_writel(0x0000d843, CSCR_U(1));
__raw_writel(0x22252521, CSCR_L(1));
__raw_writel(0x22220a00, CSCR_A(1));
}
static void __init pcm038_init(void)
{
gpio_fec_active();
pcm038_init_sram();
mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */
mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));

14
arch/arm/mach-mx3/Kconfig
View File

@ -21,5 +21,19 @@ config MACH_MX31LITE
Include support for MX31 LITEKIT platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31_3DS
bool "Support MX31PDK (3DS)"
default n
help
Include support for MX31PDK (3DS) platform. This includes specific
configurations for the board and its peripherals.
config MACH_MX31MOBOARD
bool "Support mx31moboard platforms (EPFL Mobots group)"
default n
help
Include support for mx31moboard platform. This includes specific
configurations for the board and its peripherals.
endmenu

2
arch/arm/mach-mx3/Makefile
View File

@ -8,3 +8,5 @@ obj-y := mm.o clock.o devices.o iomux.o
obj-$(CONFIG_MACH_MX31ADS) += mx31ads.o
obj-$(CONFIG_MACH_MX31LITE) += mx31lite.o
obj-$(CONFIG_MACH_PCM037) += pcm037.o
obj-$(CONFIG_MACH_MX31_3DS) += mx31pdk.o
obj-$(CONFIG_MACH_MX31MOBOARD) += mx31moboard.o

19
arch/arm/mach-mx3/devices.c
View File

@ -160,3 +160,22 @@ struct platform_device mxc_w1_master_device = {
.num_resources = ARRAY_SIZE(mxc_w1_master_resources),
.resource = mxc_w1_master_resources,
};
static struct resource mxc_nand_resources[] = {
{
.start = NFC_BASE_ADDR,
.end = NFC_BASE_ADDR + 0xfff,
.flags = IORESOURCE_MEM
}, {
.start = MXC_INT_NANDFC,
.end = MXC_INT_NANDFC,
.flags = IORESOURCE_IRQ
},
};
struct platform_device mxc_nand_device = {
.name = "mxc_nand",
.id = 0,
.num_resources = ARRAY_SIZE(mxc_nand_resources),
.resource = mxc_nand_resources,
};

1
arch/arm/mach-mx3/devices.h
View File

@ -5,3 +5,4 @@ extern struct platform_device mxc_uart_device2;
extern struct platform_device mxc_uart_device3;
extern struct platform_device mxc_uart_device4;
extern struct platform_device mxc_w1_master_device;
extern struct platform_device mxc_nand_device;

9
arch/arm/mach-mx3/iomux.c
View File

@ -74,17 +74,18 @@ void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
u32 field, l;
void __iomem *reg;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3;
pin &= IOMUX_PADNUM_MASK;
reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
field = (pin + 2) % 3;
pr_debug("%s: reg offset = 0x%x field = %d\n",
pr_debug("%s: reg offset = 0x%x, field = %d\n",
__func__, (pin + 2) / 3, field);
spin_lock(&gpio_mux_lock);
l = __raw_readl(reg);
l &= ~(0x1ff << (field * 9));
l |= config << (field * 9);
l &= ~(0x1ff << (field * 10));
l |= config << (field * 10);
__raw_writel(l, reg);
spin_unlock(&gpio_mux_lock);

141
arch/arm/mach-mx3/mx31moboard.c 100644
View File

@ -0,0 +1,141 @@
/*
* Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/partitions.h>
#include <linux/memory.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include "devices.h"
static struct physmap_flash_data mx31moboard_flash_data = {
.width = 2,
};
static struct resource mx31moboard_flash_resource = {
.start = 0xa0000000,
.end = 0xa1ffffff,
.flags = IORESOURCE_MEM,
};
static struct platform_device mx31moboard_flash = {
.name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &mx31moboard_flash_data,
},
.resource = &mx31moboard_flash_resource,
.num_resources = 1,
};
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct platform_device *devices[] __initdata = {
&mx31moboard_flash,
};
/*
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
platform_add_devices(devices, ARRAY_SIZE(devices));
mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
mxc_register_device(&mxc_uart_device0, &uart_pdata);
mxc_iomux_mode(MX31_PIN_CTS2__CTS2);
mxc_iomux_mode(MX31_PIN_RTS2__RTS2);
mxc_iomux_mode(MX31_PIN_TXD2__TXD2);
mxc_iomux_mode(MX31_PIN_RXD2__RXD2);
mxc_register_device(&mxc_uart_device1, &uart_pdata);
mxc_iomux_mode(MX31_PIN_PC_RST__CTS5);
mxc_iomux_mode(MX31_PIN_PC_VS2__RTS5);
mxc_iomux_mode(MX31_PIN_PC_BVD2__TXD5);
mxc_iomux_mode(MX31_PIN_PC_BVD1__RXD5);
mxc_register_device(&mxc_uart_device4, &uart_pdata);
}
/*
* This structure defines static mappings for the mx31moboard.
*/
static struct map_desc mx31moboard_io_desc[] __initdata = {
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
},
};
/*
* Set up static virtual mappings.
*/
void __init mx31moboard_map_io(void)
{
mxc_map_io();
iotable_init(mx31moboard_io_desc, ARRAY_SIZE(mx31moboard_io_desc));
}
static void __init mx31moboard_timer_init(void)
{
mxc_clocks_init(26000000);
mxc_timer_init("ipg_clk.0");
}
struct sys_timer mx31moboard_timer = {
.init = mx31moboard_timer_init,
};
MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
/* Maintainer: Valentin Longchamp, EPFL Mobots group */
.phys_io = AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31moboard_map_io,
.init_irq = mxc_init_irq,
.init_machine = mxc_board_init,
.timer = &mx31moboard_timer,
MACHINE_END

115
arch/arm/mach-mx3/mx31pdk.c 100644
View File

@ -0,0 +1,115 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include <linux/types.h>
#include <linux/init.h>
#include <linux/clk.h>
#include <linux/irq.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/board-mx31pdk.h>
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include "devices.h"
/*!
* @file mx31pdk.c
*
* @brief This file contains the board-specific initialization routines.
*
* @ingroup System
*/
static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
static inline void mxc_init_imx_uart(void)
{
mxc_iomux_mode(MX31_PIN_CTS1__CTS1);
mxc_iomux_mode(MX31_PIN_RTS1__RTS1);
mxc_iomux_mode(MX31_PIN_TXD1__TXD1);
mxc_iomux_mode(MX31_PIN_RXD1__RXD1);
mxc_register_device(&mxc_uart_device0, &uart_pdata);
}
/*!
* This structure defines static mappings for the i.MX31PDK board.
*/
static struct map_desc mx31pdk_io_desc[] __initdata = {
{
.virtual = AIPS1_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
.length = AIPS1_SIZE,
.type = MT_DEVICE_NONSHARED
}, {
.virtual = AIPS2_BASE_ADDR_VIRT,
.pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
.length = AIPS2_SIZE,
.type = MT_DEVICE_NONSHARED
},
};
/*!
* Set up static virtual mappings.
*/
static void __init mx31pdk_map_io(void)
{
mxc_map_io();
iotable_init(mx31pdk_io_desc, ARRAY_SIZE(mx31pdk_io_desc));
}
/*!
* Board specific initialization.
*/
static void __init mxc_board_init(void)
{
mxc_init_imx_uart();
}
static void __init mx31pdk_timer_init(void)
{
mxc_clocks_init(26000000);
mxc_timer_init("ipg_clk.0");
}
static struct sys_timer mx31pdk_timer = {
.init = mx31pdk_timer_init,
};
/*
* The following uses standard kernel macros defined in arch.h in order to
* initialize __mach_desc_MX31PDK data structure.
*/
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */
.phys_io = AIPS1_BASE_ADDR,
.io_pg_offst = ((AIPS1_BASE_ADDR_VIRT) >> 18) & 0xfffc,
.boot_params = PHYS_OFFSET + 0x100,
.map_io = mx31pdk_map_io,
.init_irq = mxc_init_irq,
.init_machine = mxc_board_init,
.timer = &mx31pdk_timer,
MACHINE_END

67
arch/arm/mach-mx3/pcm037.c
View File

@ -21,7 +21,11 @@
#include <linux/platform_device.h>
#include <linux/mtd/physmap.h>
#include <linux/mtd/plat-ram.h>
#include <linux/memory.h>
#include <linux/gpio.h>
#include <linux/smc911x.h>
#include <linux/interrupt.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
@ -32,6 +36,7 @@
#include <mach/imx-uart.h>
#include <mach/iomux-mx3.h>
#include <mach/board-pcm037.h>
#include <mach/mxc_nand.h>
#include "devices.h"
@ -59,8 +64,63 @@ static struct imxuart_platform_data uart_pdata = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct resource smc911x_resources[] = {
[0] = {
.start = CS1_BASE_ADDR + 0x300,
.end = CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
.end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
.flags = IORESOURCE_IRQ,
},
};
static struct smc911x_platdata smc911x_info = {
.flags = SMC911X_USE_32BIT,
.irq_flags = IRQF_SHARED | IRQF_TRIGGER_LOW,
};
static struct platform_device pcm037_eth = {
.name = "smc911x",
.id = -1,
.num_resources = ARRAY_SIZE(smc911x_resources),
.resource = smc911x_resources,
.dev = {
.platform_data = &smc911x_info,
},
};
static struct platdata_mtd_ram pcm038_sram_data = {
.bankwidth = 2,
};
static struct resource pcm038_sram_resource = {
.start = CS4_BASE_ADDR,
.end = CS4_BASE_ADDR + 512 * 1024 - 1,
.flags = IORESOURCE_MEM,
};
static struct platform_device pcm037_sram_device = {
.name = "mtd-ram",
.id = 0,
.dev = {
.platform_data = &pcm038_sram_data,
},
.num_resources = 1,
.resource = &pcm038_sram_resource,
};
static struct mxc_nand_platform_data pcm037_nand_board_info = {
.width = 1,
.hw_ecc = 1,
};
static struct platform_device *devices[] __initdata = {
&pcm037_flash,
&pcm037_eth,
&pcm037_sram_device,
};
/*
@ -84,6 +144,13 @@ static void __init mxc_board_init(void)
mxc_iomux_mode(MX31_PIN_BATT_LINE__OWIRE);
mxc_register_device(&mxc_w1_master_device, NULL);
/* SMSC9215 IRQ pin */
mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO));
if (!gpio_request(MX31_PIN_GPIO3_1, "pcm037-eth"))
gpio_direction_input(MX31_PIN_GPIO3_1);
mxc_register_device(&mxc_nand_device, &pcm037_nand_board_info);
}
/*

6
arch/arm/plat-mxc/Kconfig
View File

@ -6,6 +6,11 @@ choice
prompt "MXC/iMX Base Type"
default ARCH_MX3
config ARCH_MX1
bool "MX1-based"
help
This enables support for systems based on the Freescale i.MX1 family
config ARCH_MX2
bool "MX2-based"
select CPU_ARM926T
@ -20,6 +25,7 @@ config ARCH_MX3
endchoice
source "arch/arm/mach-mx1/Kconfig"
source "arch/arm/mach-mx2/Kconfig"
source "arch/arm/mach-mx3/Kconfig"

1
arch/arm/plat-mxc/Makefile
View File

@ -5,4 +5,5 @@
# Common support
obj-y := irq.o clock.o gpio.o time.o devices.o
obj-$(CONFIG_ARCH_MX1) += iomux-mx1-mx2.o dma-mx1-mx2.o
obj-$(CONFIG_ARCH_MX2) += iomux-mx1-mx2.o dma-mx1-mx2.o

7
arch/arm/plat-mxc/dma-mx1-mx2.c
View File

@ -34,7 +34,6 @@
#include <asm/system.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include <mach/dma-mx1-mx2.h>
#define DMA_DCR 0x00 /* Control Register */
@ -114,7 +113,7 @@ struct imx_dma_channel {
void (*err_handler) (int, void *, int errcode);
void (*prog_handler) (int, void *, struct scatterlist *);
void *data;
dmamode_t dma_mode;
unsigned int dma_mode;
struct scatterlist *sg;
unsigned int resbytes;
int dma_num;
@ -193,7 +192,7 @@ static inline int imx_dma_sg_next(int channel, struct scatterlist *sg)
int
imx_dma_setup_single(int channel, dma_addr_t dma_address,
unsigned int dma_length, unsigned int dev_addr,
dmamode_t dmamode)
unsigned int dmamode)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];
@ -288,7 +287,7 @@ int
imx_dma_setup_sg(int channel,
struct scatterlist *sg, unsigned int sgcount,
unsigned int dma_length, unsigned int dev_addr,
dmamode_t dmamode)
unsigned int dmamode)
{
struct imx_dma_channel *imxdma = &imx_dma_channels[channel];

6
arch/arm/plat-mxc/gpio.c
View File

@ -115,8 +115,8 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
}
}
#ifdef CONFIG_ARCH_MX3
/* MX3 has one interrupt *per* gpio port */
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
/* MX1 and MX3 has one interrupt *per* gpio port */
static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{
u32 irq_stat;
@ -237,7 +237,7 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
/* its a serious configuration bug when it fails */
BUG_ON( gpiochip_add(&port[i].chip) < 0 );
#ifdef CONFIG_ARCH_MX3
#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX1)
/* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]);

5
arch/arm/plat-mxc/include/mach/board-mx27ads.h
View File

@ -28,11 +28,6 @@
/*
* MXC UART EVB board level configurations
*/
#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
#define MXC_LL_EXTUART_16BIT_BUS
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)

19
arch/arm/plat-mxc/include/mach/board-mx31pdk.h 100644
View File

@ -0,0 +1,19 @@
/*
* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_BOARD_MX31PDK_H__
#define __ASM_ARCH_MXC_BOARD_MX31PDK_H__
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_BOARD_MX31PDK_H__ */

3
arch/arm/plat-mxc/include/mach/debug-macro.S
View File

@ -27,6 +27,9 @@
#endif
#ifdef CONFIG_MACH_PCM038
#include <mach/board-pcm038.h>
#endif
#ifdef CONFIG_MACH_MX31_3DS
#include <mach/board-mx31pdk.h>
#endif
.macro addruart,rx
mrc p15, 0, \rx, c1, c0

10
arch/arm/plat-mxc/include/mach/dma-mx1-mx2.h
View File

@ -22,13 +22,15 @@
* MA 02110-1301, USA.
*/
#include <mach/dma.h>
#ifndef __ASM_ARCH_MXC_DMA_H
#define __ASM_ARCH_MXC_DMA_H
#define IMX_DMA_CHANNELS 16
#define DMA_MODE_READ 0
#define DMA_MODE_WRITE 1
#define DMA_MODE_MASK 1
#define DMA_BASE IO_ADDRESS(DMA_BASE_ADDR)
#define IMX_DMA_MEMSIZE_32 (0 << 4)
@ -54,12 +56,12 @@ imx_dma_config_burstlen(int channel, unsigned int burstlen);
int
imx_dma_setup_single(int channel, dma_addr_t dma_address,
unsigned int dma_length, unsigned int dev_addr,
dmamode_t dmamode);
unsigned int dmamode);
int
imx_dma_setup_sg(int channel, struct scatterlist *sg,
unsigned int sgcount, unsigned int dma_length,
unsigned int dev_addr, dmamode_t dmamode);
unsigned int dev_addr, unsigned int dmamode);
int
imx_dma_setup_handlers(int channel,

4
arch/arm/plat-mxc/include/mach/hardware.h
View File

@ -32,6 +32,10 @@
# endif
#endif
#ifdef CONFIG_ARCH_MX1
# include <mach/mx1.h>
#endif
#include <mach/mxc.h>
#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */

68
arch/arm/plat-mxc/include/mach/iomux-mx1-mx2.h
View File

@ -21,12 +21,6 @@
#include <linux/io.h>
#define MXC_GPIO_ALLOC_MODE_NORMAL 0
#define MXC_GPIO_ALLOC_MODE_NO_ALLOC 1
#define MXC_GPIO_ALLOC_MODE_TRY_ALLOC 2
#define MXC_GPIO_ALLOC_MODE_ALLOC_ONLY 4
#define MXC_GPIO_ALLOC_MODE_RELEASE 8
/*
* GPIO Module and I/O Multiplexer
* x = 0..3 for reg_A, reg_B, reg_C, reg_D
@ -103,7 +97,8 @@
extern void mxc_gpio_mode(int gpio_mode);
extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
int alloc_mode, const char *label);
const char *label);
extern void mxc_gpio_release_multiple_pins(const int *pin_list, int count);
/*-------------------------------------------------------------------------*/
@ -113,9 +108,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
* missing on some (many) pins
*/
#ifdef CONFIG_ARCH_MX1
#define PA0_AIN_SPI2_CLK (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 0)
#define PA0_AIN_SPI2_CLK (GPIO_PORTA | GPIO_OUT | 0)
#define PA0_AF_ETMTRACESYNC (GPIO_PORTA | GPIO_AF | 0)
#define PA1_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTA | GPIO_IN | 1)
#define PA1_AOUT_SPI2_RXD (GPIO_PORTA | GPIO_IN | 1)
#define PA1_PF_TIN (GPIO_PORTA | GPIO_PF | 1)
#define PA2_PF_PWM0 (GPIO_PORTA | GPIO_OUT | GPIO_PF | 2)
#define PA3_PF_CSI_MCLK (GPIO_PORTA | GPIO_PF | 3)
@ -133,7 +128,7 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PA15_PF_I2C_SDA (GPIO_PORTA | GPIO_OUT | GPIO_PF | 15)
#define PA16_PF_I2C_SCL (GPIO_PORTA | GPIO_OUT | GPIO_PF | 16)
#define PA17_AF_ETMTRACEPKT4 (GPIO_PORTA | GPIO_AF | 17)
#define PA17_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTA | GPIO_OUT | 17)
#define PA17_AIN_SPI2_SS (GPIO_PORTA | GPIO_OUT | 17)
#define PA18_AF_ETMTRACEPKT5 (GPIO_PORTA | GPIO_AF | 18)
#define PA19_AF_ETMTRACEPKT6 (GPIO_PORTA | GPIO_AF | 19)
#define PA20_AF_ETMTRACEPKT7 (GPIO_PORTA | GPIO_AF | 20)
@ -201,27 +196,27 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PC15_PF_SPI1_SS (GPIO_PORTC | GPIO_PF | 15)
#define PC16_PF_SPI1_MISO (GPIO_PORTC | GPIO_PF | 16)
#define PC17_PF_SPI1_MOSI (GPIO_PORTC | GPIO_PF | 17)
#define PC24_BIN_UART3_RI (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
#define PC25_BIN_UART3_DSR (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
#define PC26_AOUT_UART3_DTR (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 26)
#define PC27_BIN_UART3_DCD (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
#define PC28_BIN_UART3_CTS (GPIO_GIUS | GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
#define PC29_AOUT_UART3_RTS (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 29)
#define PC30_BIN_UART3_TX (GPIO_GIUS | GPIO_PORTC | GPIO_BIN | 30)
#define PC31_AOUT_UART3_RX (GPIO_GIUS | GPIO_PORTC | GPIO_IN | 31)
#define PC24_BIN_UART3_RI (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 24)
#define PC25_BIN_UART3_DSR (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 25)
#define PC26_AOUT_UART3_DTR (GPIO_PORTC | GPIO_IN | 26)
#define PC27_BIN_UART3_DCD (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 27)
#define PC28_BIN_UART3_CTS (GPIO_PORTC | GPIO_OUT | GPIO_BIN | 28)
#define PC29_AOUT_UART3_RTS (GPIO_PORTC | GPIO_IN | 29)
#define PC30_BIN_UART3_TX (GPIO_PORTC | GPIO_BIN | 30)
#define PC31_AOUT_UART3_RX (GPIO_PORTC | GPIO_IN | 31)
#define PD6_PF_LSCLK (GPIO_PORTD | GPIO_OUT | GPIO_PF | 6)
#define PD7_PF_REV (GPIO_PORTD | GPIO_PF | 7)
#define PD7_AF_UART2_DTR (GPIO_GIUS | GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
#define PD7_AIN_SPI2_SCLK (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 7)
#define PD7_AF_UART2_DTR (GPIO_PORTD | GPIO_IN | GPIO_AF | 7)
#define PD7_AIN_SPI2_SCLK (GPIO_PORTD | GPIO_AIN | 7)
#define PD8_PF_CLS (GPIO_PORTD | GPIO_PF | 8)
#define PD8_AF_UART2_DCD (GPIO_PORTD | GPIO_OUT | GPIO_AF | 8)
#define PD8_AIN_SPI2_SS (GPIO_GIUS | GPIO_PORTD | GPIO_AIN | 8)
#define PD8_AIN_SPI2_SS (GPIO_PORTD | GPIO_AIN | 8)
#define PD9_PF_PS (GPIO_PORTD | GPIO_PF | 9)
#define PD9_AF_UART2_RI (GPIO_PORTD | GPIO_OUT | GPIO_AF | 9)
#define PD9_AOUT_SPI2_RXD (GPIO_GIUS | GPIO_PORTD | GPIO_IN | 9)
#define PD9_AOUT_SPI2_RXD (GPIO_PORTD | GPIO_IN | 9)
#define PD10_PF_SPL_SPR (GPIO_PORTD | GPIO_OUT | GPIO_PF | 10)
#define PD10_AF_UART2_DSR (GPIO_PORTD | GPIO_OUT | GPIO_AF | 10)
#define PD10_AIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_OUT | 10)
#define PD10_AIN_SPI2_TXD (GPIO_PORTD | GPIO_OUT | 10)
#define PD11_PF_CONTRAST (GPIO_PORTD | GPIO_OUT | GPIO_PF | 11)
#define PD12_PF_ACD_OE (GPIO_PORTD | GPIO_OUT | GPIO_PF | 12)
#define PD13_PF_LP_HSYNC (GPIO_PORTD | GPIO_OUT | GPIO_PF | 13)
@ -243,7 +238,7 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PD29_PF_LD14 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 29)
#define PD30_PF_LD15 (GPIO_PORTD | GPIO_OUT | GPIO_PF | 30)
#define PD31_PF_TMR2OUT (GPIO_PORTD | GPIO_PF | 31)
#define PD31_BIN_SPI2_TXD (GPIO_GIUS | GPIO_PORTD | GPIO_BIN | 31)
#define PD31_BIN_SPI2_TXD (GPIO_PORTD | GPIO_BIN | 31)
#endif
#ifdef CONFIG_ARCH_MX2
@ -279,6 +274,12 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PA29_PF_VSYNC (GPIO_PORTA | GPIO_OUT | GPIO_PF | 29)
#define PA30_PF_CONTRAST (GPIO_PORTA | GPIO_OUT | GPIO_PF | 30)
#define PA31_PF_OE_ACD (GPIO_PORTA | GPIO_OUT | GPIO_PF | 31)
#define PB4_PF_SD2_D0 (GPIO_PORTB | GPIO_PF | 4)
#define PB5_PF_SD2_D1 (GPIO_PORTB | GPIO_PF | 5)
#define PB6_PF_SD2_D2 (GPIO_PORTB | GPIO_PF | 6)
#define PB7_PF_SD2_D3 (GPIO_PORTB | GPIO_PF | 7)
#define PB8_PF_SD2_CMD (GPIO_PORTB | GPIO_PF | 8)
#define PB9_PF_SD2_CLK (GPIO_PORTB | GPIO_PF | 9)
#define PB10_PF_CSI_D0 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 10)
#define PB10_AF_UART6_TXD (GPIO_PORTB | GPIO_OUT | GPIO_AF | 10)
#define PB11_PF_CSI_D1 (GPIO_PORTB | GPIO_OUT | GPIO_PF | 11)
@ -315,6 +316,13 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PB31_AF_UART4_RXD (GPIO_PORTB | GPIO_IN | GPIO_AF | 31)
#define PC5_PF_I2C2_SDA (GPIO_PORTC | GPIO_IN | GPIO_PF | 5)
#define PC6_PF_I2C2_SCL (GPIO_PORTC | GPIO_IN | GPIO_PF | 6)
#define PC7_PF_USBOTG_DATA5 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 7)
#define PC8_PF_USBOTG_DATA6 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 8)
#define PC9_PF_USBOTG_DATA0 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 9)
#define PC10_PF_USBOTG_DATA2 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 10)
#define PC11_PF_USBOTG_DATA1 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 11)
#define PC12_PF_USBOTG_DATA4 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 12)
#define PC13_PF_USBOTG_DATA3 (GPIO_PORTC | GPIO_OUT | GPIO_PF | 13)
#define PC16_PF_SSI4_FS (GPIO_PORTC | GPIO_IN | GPIO_PF | 16)
#define PC17_PF_SSI4_RXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 17)
#define PC18_PF_SSI4_TXD (GPIO_PORTC | GPIO_IN | GPIO_PF | 18)
@ -365,6 +373,9 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PD30_PF_CSPI1_MISO (GPIO_PORTD | GPIO_IN | GPIO_PF | 30)
#define PD31_PF_CSPI1_MOSI (GPIO_PORTD | GPIO_OUT | GPIO_PF | 31)
#define PF23_AIN_FEC_TX_EN (GPIO_PORTF | GPIO_OUT | GPIO_AIN | 23)
#define PE0_PF_USBOTG_NXT (GPIO_PORTE | GPIO_OUT | GPIO_PF | 0)
#define PE1_PF_USBOTG_STP (GPIO_PORTE | GPIO_OUT | GPIO_PF | 1)
#define PE2_PF_USBOTG_DIR (GPIO_PORTE | GPIO_OUT | GPIO_PF | 2)
#define PE3_PF_UART2_CTS (GPIO_PORTE | GPIO_OUT | GPIO_PF | 3)
#define PE4_PF_UART2_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 4)
#define PE6_PF_UART2_TXD (GPIO_PORTE | GPIO_OUT | GPIO_PF | 6)
@ -379,10 +390,18 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define PE15_PF_UART1_RTS (GPIO_PORTE | GPIO_IN | GPIO_PF | 15)
#define PE16_AF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 16)
#define PE16_PF_RTCK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 16)
#define PE18_PF_SDHC1_D0 (GPIO_PORTE | GPIO_PF | 18)
#define PE18_AF_CSPI3_MISO (GPIO_PORTE | GPIO_IN | GPIO_AF | 18)
#define PE19_PF_SDHC1_D1 (GPIO_PORTE | GPIO_PF | 19)
#define PE20_PF_SDHC1_D2 (GPIO_PORTE | GPIO_PF | 20)
#define PE21_PF_SDHC1_D3 (GPIO_PORTE | GPIO_PF | 21)
#define PE21_AF_CSPI3_SS (GPIO_PORTE | GPIO_OUT | GPIO_AF | 21)
#define PE22_PF_SDHC1_CMD (GPIO_PORTE | GPIO_PF | 22)
#define PE22_AF_CSPI3_MOSI (GPIO_PORTE | GPIO_OUT | GPIO_AF | 22)
#define PE22_PF_SDHC1_CLK (GPIO_PORTE | GPIO_PF | 23)
#define PE23_AF_CSPI3_SCLK (GPIO_PORTE | GPIO_OUT | GPIO_AF | 23)
#define PE24_PF_USBOTG_CLK (GPIO_PORTE | GPIO_OUT | GPIO_PF | 24)
#define PE25_PF_USBOTG_DATA7 (GPIO_PORTE | GPIO_OUT | GPIO_PF | 25)
#endif
/* decode irq number to use with IMR(x), ISR(x) and friends */
@ -392,5 +411,6 @@ extern int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
#define IRQ_GPIOB(x) (IRQ_GPIOA(32) + x)
#define IRQ_GPIOC(x) (IRQ_GPIOB(32) + x)
#define IRQ_GPIOD(x) (IRQ_GPIOC(32) + x)
#define IRQ_GPIOE(x) (IRQ_GPIOD(32) + x)
#endif /* _MXC_GPIO_MX1_MX2_H */

17
arch/arm/plat-mxc/include/mach/iomux-mx3.h
View File

@ -491,6 +491,14 @@ enum iomux_pins {
#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RXD2__RXD2 IOMUX_MODE(MX31_PIN_RXD2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_PC_RST__CTS5 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT2)
#define MX31_PIN_PC_VS2__RTS5 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT2)
#define MX31_PIN_PC_BVD2__TXD5 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT2)
#define MX31_PIN_PC_BVD1__RXD5 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_CSPI1_MOSI__MOSI IOMUX_MODE(MX31_PIN_CSPI1_MOSI, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI1_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI1_MISO, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI1_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI1_SCLK, IOMUX_CONFIG_FUNC)
@ -509,6 +517,15 @@ enum iomux_pins {
#define MX31_PIN_CSPI3_MISO__MISO IOMUX_MODE(MX31_PIN_CSPI3_MISO, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI3_SCLK__SCLK IOMUX_MODE(MX31_PIN_CSPI3_SCLK, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CSPI3_SPI_RDY__SPI_RDY IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_FUNC)
#define MX31_PIN_BATT_LINE__OWIRE IOMUX_MODE(MX31_PIN_BATT_LINE, IOMUX_CONFIG_FUNC)
#define MX31_PIN_CS4__CS4 IOMUX_MODE(MX31_PIN_CS4, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_DATA3__SD1_DATA3 IOMUX_MODE(MX31_PIN_SD1_DATA3, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_DATA2__SD1_DATA2 IOMUX_MODE(MX31_PIN_SD1_DATA2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_DATA1__SD1_DATA1 IOMUX_MODE(MX31_PIN_SD1_DATA1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_DATA0__SD1_DATA0 IOMUX_MODE(MX31_PIN_SD1_DATA0, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_CLK__SD1_CLK IOMUX_MODE(MX31_PIN_SD1_CLK, IOMUX_CONFIG_FUNC)
#define MX31_PIN_SD1_CMD__SD1_CMD IOMUX_MODE(MX31_PIN_SD1_CMD, IOMUX_CONFIG_FUNC)
/*XXX: The SS0, SS1, SS2, SS3 lines of spi3 are multiplexed by cspi2_ss0, cspi2_ss1, cspi1_ss0
* cspi1_ss1*/

5
arch/arm/plat-mxc/include/mach/irqs.h
View File

@ -14,4 +14,9 @@
#include <mach/hardware.h>
extern void imx_irq_set_priority(unsigned char irq, unsigned char prio);
/* all normal IRQs can be FIQs */
#define FIQ_START 0
/* switch betwean IRQ and FIQ */
extern int mxc_set_irq_fiq(unsigned int irq, unsigned int type);
#endif /* __ASM_ARCH_MXC_IRQS_H__ */

34
arch/arm/plat-mxc/include/mach/mtd-xip.h 100644
View File

@ -0,0 +1,34 @@
/*
* MTD primitives for XIP support. Architecture specific functions
*
* Do not include this file directly. It's included from linux/mtd/xip.h
*
* Copyright (C) 2008 Darius Augulis <augulis.darius@gmail.com>, Teltonika, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#include <mach/mxc_timer.h>
#ifndef __ARCH_IMX_MTD_XIP_H__
#define __ARCH_IMX_MTD_XIP_H__
#ifdef CONFIG_ARCH_MX1
/* AITC registers */
#define AITC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
#define NIPNDH (AITC_BASE + 0x58)
#define NIPNDL (AITC_BASE + 0x5C)
#define INTENABLEH (AITC_BASE + 0x10)
#define INTENABLEL (AITC_BASE + 0x14)
/* MTD macros */
#define xip_irqpending() ((__raw_readl(INTENABLEH) & __raw_readl(NIPNDH)) \
|| (__raw_readl(INTENABLEL) & __raw_readl(NIPNDL)))
#define xip_currtime() (__raw_readl(TIMER_BASE + MXC_TCN))
#define xip_elapsed_since(x) (signed)((__raw_readl(TIMER_BASE + MXC_TCN) - (x)) / 96)
#define xip_cpu_idle() asm volatile ("mcr p15, 0, %0, c7, c0, 4" :: "r" (0))
#endif /* CONFIG_ARCH_MX1 */
#endif /* __ARCH_IMX_MTD_XIP_H__ */

197
arch/arm/plat-mxc/include/mach/mx1.h 100644
View File

@ -0,0 +1,197 @@
/*
* Copyright (C) 1997,1998 Russell King
* Copyright (C) 1999 ARM Limited
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_MXC_MX1_H__
#define __ASM_ARCH_MXC_MX1_H__
#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#error "Do not include directly."
#endif
#include <mach/vmalloc.h>
/*
* defines the hardware clock tick rate
*/
#define CLOCK_TICK_RATE 16000000
#define PHYS_OFFSET UL(0x08000000)
/*
* Memory map
*/
#define IMX_IO_PHYS 0x00200000
#define IMX_IO_SIZE 0x00100000
#define IMX_IO_BASE VMALLOC_END
#define IMX_CS0_PHYS 0x10000000
#define IMX_CS0_SIZE 0x02000000
#define IMX_CS1_PHYS 0x12000000
#define IMX_CS1_SIZE 0x01000000
#define IMX_CS2_PHYS 0x13000000
#define IMX_CS2_SIZE 0x01000000
#define IMX_CS3_PHYS 0x14000000
#define IMX_CS3_SIZE 0x01000000
#define IMX_CS4_PHYS 0x15000000
#define IMX_CS4_SIZE 0x01000000
#define IMX_CS5_PHYS 0x16000000
#define IMX_CS5_SIZE 0x01000000
/*
* Register BASEs, based on OFFSETs
*/
#define AIPI1_BASE_ADDR (0x00000 + IMX_IO_PHYS)
#define WDT_BASE_ADDR (0x01000 + IMX_IO_PHYS)
#define TIM1_BASE_ADDR (0x02000 + IMX_IO_PHYS)
#define TIM2_BASE_ADDR (0x03000 + IMX_IO_PHYS)
#define RTC_BASE_ADDR (0x04000 + IMX_IO_PHYS)
#define LCDC_BASE_ADDR (0x05000 + IMX_IO_PHYS)
#define UART1_BASE_ADDR (0x06000 + IMX_IO_PHYS)
#define UART2_BASE_ADDR (0x07000 + IMX_IO_PHYS)
#define PWM_BASE_ADDR (0x08000 + IMX_IO_PHYS)
#define DMA_BASE_ADDR (0x09000 + IMX_IO_PHYS)
#define AIPI2_BASE_ADDR (0x10000 + IMX_IO_PHYS)
#define SIM_BASE_ADDR (0x11000 + IMX_IO_PHYS)
#define USBD_BASE_ADDR (0x12000 + IMX_IO_PHYS)
#define SPI1_BASE_ADDR (0x13000 + IMX_IO_PHYS)
#define MMC_BASE_ADDR (0x14000 + IMX_IO_PHYS)
#define ASP_BASE_ADDR (0x15000 + IMX_IO_PHYS)
#define BTA_BASE_ADDR (0x16000 + IMX_IO_PHYS)
#define I2C_BASE_ADDR (0x17000 + IMX_IO_PHYS)
#define SSI_BASE_ADDR (0x18000 + IMX_IO_PHYS)
#define SPI2_BASE_ADDR (0x19000 + IMX_IO_PHYS)
#define MSHC_BASE_ADDR (0x1A000 + IMX_IO_PHYS)
#define CCM_BASE_ADDR (0x1B000 + IMX_IO_PHYS)
#define SCM_BASE_ADDR (0x1B804 + IMX_IO_PHYS)
#define GPIO_BASE_ADDR (0x1C000 + IMX_IO_PHYS)
#define EIM_BASE_ADDR (0x20000 + IMX_IO_PHYS)
#define SDRAMC_BASE_ADDR (0x21000 + IMX_IO_PHYS)
#define MMA_BASE_ADDR (0x22000 + IMX_IO_PHYS)
#define AVIC_BASE_ADDR (0x23000 + IMX_IO_PHYS)
#define CSI_BASE_ADDR (0x24000 + IMX_IO_PHYS)
/* macro to get at IO space when running virtually */
#define IO_ADDRESS(x) ((x) - IMX_IO_PHYS + IMX_IO_BASE)
/* define macros needed for entry-macro.S */
#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
/* fixed interrput numbers */
#define INT_SOFTINT 0
#define CSI_INT 6
#define DSPA_MAC_INT 7
#define DSPA_INT 8
#define COMP_INT 9
#define MSHC_XINT 10
#define GPIO_INT_PORTA 11
#define GPIO_INT_PORTB 12
#define GPIO_INT_PORTC 13
#define LCDC_INT 14
#define SIM_INT 15
#define SIM_DATA_INT 16
#define RTC_INT 17
#define RTC_SAMINT 18
#define UART2_MINT_PFERR 19
#define UART2_MINT_RTS 20
#define UART2_MINT_DTR 21
#define UART2_MINT_UARTC 22
#define UART2_MINT_TX 23
#define UART2_MINT_RX 24
#define UART1_MINT_PFERR 25
#define UART1_MINT_RTS 26
#define UART1_MINT_DTR 27
#define UART1_MINT_UARTC 28
#define UART1_MINT_TX 29
#define UART1_MINT_RX 30
#define VOICE_DAC_INT 31
#define VOICE_ADC_INT 32
#define PEN_DATA_INT 33
#define PWM_INT 34
#define SDHC_INT 35
#define I2C_INT 39
#define CSPI_INT 41
#define SSI_TX_INT 42
#define SSI_TX_ERR_INT 43
#define SSI_RX_INT 44
#define SSI_RX_ERR_INT 45
#define TOUCH_INT 46
#define USBD_INT0 47
#define USBD_INT1 48
#define USBD_INT2 49
#define USBD_INT3 50
#define USBD_INT4 51
#define USBD_INT5 52
#define USBD_INT6 53
#define BTSYS_INT 55
#define BTTIM_INT 56
#define BTWUI_INT 57
#define TIM2_INT 58
#define TIM1_INT 59
#define DMA_ERR 60
#define DMA_INT 61
#define GPIO_INT_PORTD 62
#define WDT_INT 63
#define MXC_MAX_INT_LINES 64
#define NR_IRQS 256
/* gpio and gpio based interrupt handling */
#define GPIO_DR 0x1C
#define GPIO_GDIR 0x00
#define GPIO_PSR 0x24
#define GPIO_ICR1 0x28
#define GPIO_ICR2 0x2C
#define GPIO_IMR 0x30
#define GPIO_ISR 0x34
#define GPIO_INT_LOW_LEV 0x3
#define GPIO_INT_HIGH_LEV 0x2
#define GPIO_INT_RISE_EDGE 0x0
#define GPIO_INT_FALL_EDGE 0x1
#define GPIO_INT_NONE 0x4
/* DMA */
#define DMA_REQ_UART3_T 2
#define DMA_REQ_UART3_R 3
#define DMA_REQ_SSI2_T 4
#define DMA_REQ_SSI2_R 5
#define DMA_REQ_CSI_STAT 6
#define DMA_REQ_CSI_R 7
#define DMA_REQ_MSHC 8
#define DMA_REQ_DSPA_DCT_DOUT 9
#define DMA_REQ_DSPA_DCT_DIN 10
#define DMA_REQ_DSPA_MAC 11
#define DMA_REQ_EXT 12
#define DMA_REQ_SDHC 13
#define DMA_REQ_SPI1_R 14
#define DMA_REQ_SPI1_T 15
#define DMA_REQ_SSI_T 16
#define DMA_REQ_SSI_R 17
#define DMA_REQ_ASP_DAC 18
#define DMA_REQ_ASP_ADC 19
#define DMA_REQ_USP_EP(x) (20 + (x))
#define DMA_REQ_SPI2_R 26
#define DMA_REQ_SPI2_T 27
#define DMA_REQ_UART2_T 28
#define DMA_REQ_UART2_R 29
#define DMA_REQ_UART1_T 30
#define DMA_REQ_UART1_R 31
/* mandatory for CONFIG_LL_DEBUG */
#define MXC_LL_UART_PADDR UART1_BASE_ADDR
#define MXC_LL_UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
#endif /* __ASM_ARCH_MXC_MX1_H__ */

3
arch/arm/plat-mxc/include/mach/mx27.h
View File

@ -72,7 +72,8 @@
/* for mx27*/
#define OTG_BASE_ADDR USBOTG_BASE_ADDR
#define SAHARA_BASE_ADDR (AIPI_BASE_ADDR + 0x25000)
#define EMMA_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
#define EMMA_PP_BASE_ADDR (AIPI_BASE_ADDR + 0x26000)
#define EMMA_PRP_BASE_ADDR (AIPI_BASE_ADDR + 0x26400)
#define CCM_BASE_ADDR (AIPI_BASE_ADDR + 0x27000)
#define SYSCTRL_BASE_ADDR (AIPI_BASE_ADDR + 0x27800)
#define IIM_BASE_ADDR (AIPI_BASE_ADDR + 0x28000)

4
arch/arm/plat-mxc/include/mach/mxc_timer.h
View File

@ -26,7 +26,7 @@
#include <linux/clk.h>
#include <mach/hardware.h>
#ifdef CONFIG_ARCH_IMX
#ifdef CONFIG_ARCH_MX1
#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
#define TIMER_INTERRUPT TIM1_INT
@ -65,7 +65,7 @@ static void gpt_irq_acknowledge(void)
{
__raw_writel(0, TIMER_BASE + MXC_TSTAT);
}
#endif /* CONFIG_ARCH_IMX */
#endif /* CONFIG_ARCH_MX1 */
#ifdef CONFIG_ARCH_MX2
#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)

43
arch/arm/plat-mxc/iomux-mx1-mx2.c
View File

@ -110,12 +110,13 @@ void mxc_gpio_mode(int gpio_mode)
EXPORT_SYMBOL(mxc_gpio_mode);
int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
int alloc_mode, const char *label)
const char *label)
{
const int *p = pin_list;
int i;
unsigned gpio;
unsigned mode;
int ret = -EINVAL;
for (i = 0; i < count; i++) {
gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
@ -124,33 +125,33 @@ int mxc_gpio_setup_multiple_pins(const int *pin_list, unsigned count,
if (gpio >= (GPIO_PORT_MAX + 1) * 32)
goto setup_error;
if (alloc_mode & MXC_GPIO_ALLOC_MODE_RELEASE)
gpio_free(gpio);
else if (!(alloc_mode & MXC_GPIO_ALLOC_MODE_NO_ALLOC))
if (gpio_request(gpio, label)
&& !(alloc_mode & MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
goto setup_error;
ret = gpio_request(gpio, label);
if (ret)
goto setup_error;
if (!(alloc_mode & (MXC_GPIO_ALLOC_MODE_ALLOC_ONLY |
MXC_GPIO_ALLOC_MODE_RELEASE)))
mxc_gpio_mode(gpio | mode);
mxc_gpio_mode(gpio | mode);
p++;
}
return 0;
setup_error:
if (alloc_mode & (MXC_GPIO_ALLOC_MODE_NO_ALLOC |
MXC_GPIO_ALLOC_MODE_TRY_ALLOC))
return -EINVAL;
while (p != pin_list) {
p--;
gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
gpio_free(gpio);
}
return -EINVAL;
mxc_gpio_release_multiple_pins(pin_list, i);
return ret;
}
EXPORT_SYMBOL(mxc_gpio_setup_multiple_pins);
void mxc_gpio_release_multiple_pins(const int *pin_list, int count)
{
const int *p = pin_list;
int i;
for (i = 0; i < count; i++) {
unsigned gpio = *p & (GPIO_PIN_MASK | GPIO_PORT_MASK);
gpio_free(gpio);
p++;
}
}
EXPORT_SYMBOL(mxc_gpio_release_multiple_pins);

30
arch/arm/plat-mxc/irq.c
View File

@ -17,9 +17,11 @@
* MA 02110-1301, USA.
*/
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/common.h>
#include <asm/mach/irq.h>
#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
@ -65,6 +67,28 @@ void imx_irq_set_priority(unsigned char irq, unsigned char prio)
EXPORT_SYMBOL(imx_irq_set_priority);
#endif
#ifdef CONFIG_FIQ
int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{
unsigned int irqt;
if (irq >= MXC_MAX_INT_LINES)
return -EINVAL;
if (irq < MXC_MAX_INT_LINES / 2) {
irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
} else {
irq -= MXC_MAX_INT_LINES / 2;
irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
}
return 0;
}
EXPORT_SYMBOL(mxc_set_irq_fiq);
#endif /* CONFIG_FIQ */
/* Disable interrupt number "irq" in the AVIC */
static void mxc_mask_irq(unsigned int irq)
{
@ -91,7 +115,6 @@ static struct irq_chip mxc_avic_chip = {
void __init mxc_init_irq(void)
{
int i;
u32 reg;
/* put the AVIC into the reset value with
* all interrupts disabled
@ -119,5 +142,10 @@ void __init mxc_init_irq(void)
/* init architectures chained interrupt handler */
mxc_register_gpios();
#ifdef CONFIG_FIQ
/* Initialize FIQ */
init_FIQ();
#endif
printk(KERN_INFO "MXC IRQ initialized\n");
}

459
drivers/mmc/host/imxmmc.c
View File

@ -10,20 +10,6 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* 2005-04-17 Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Changed to conform redesigned i.MX scatter gather DMA interface
*
* 2005-11-04 Pavel Pisa <pisa@cmp.felk.cvut.cz>
* Updated for 2.6.14 kernel
*
* 2005-12-13 Jay Monkman <jtm@smoothsmoothie.com>
* Found and corrected problems in the write path
*
* 2005-12-30 Pavel Pisa <pisa@cmp.felk.cvut.cz>
* The event handling rewritten right way in softirq.
* Added many ugly hacks and delays to overcome SDHC
* deficiencies
*
*/
#include <linux/module.h>
@ -37,9 +23,9 @@
#include <linux/mmc/card.h>
#include <linux/delay.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <asm/dma.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/sizes.h>
#include <mach/mmc.h>
@ -50,17 +36,16 @@
#define DRIVER_NAME "imx-mmc"
#define IMXMCI_INT_MASK_DEFAULT (INT_MASK_BUF_READY | INT_MASK_DATA_TRAN | \
INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
INT_MASK_WRITE_OP_DONE | INT_MASK_END_CMD_RES | \
INT_MASK_AUTO_CARD_DETECT | INT_MASK_DAT0_EN | INT_MASK_SDIO)
struct imxmci_host {
struct mmc_host *mmc;
spinlock_t lock;
struct resource *res;
void __iomem *base;
int irq;
imx_dmach_t dma;
unsigned int clkrt;
unsigned int cmdat;
volatile unsigned int imask;
unsigned int power_mode;
unsigned int present;
@ -74,7 +59,7 @@ struct imxmci_host {
struct tasklet_struct tasklet;
unsigned int status_reg;
unsigned long pending_events;
/* Next to fields are there for CPU driven transfers to overcome SDHC deficiencies */
/* Next two fields are there for CPU driven transfers to overcome SDHC deficiencies */
u16 *data_ptr;
unsigned int data_cnt;
atomic_t stuck_timeout;
@ -114,14 +99,22 @@ struct imxmci_host {
static void imxmci_stop_clock(struct imxmci_host *host)
{
int i = 0;
MMC_STR_STP_CLK &= ~STR_STP_CLK_START_CLK;
while(i < 0x1000) {
if(!(i & 0x7f))
MMC_STR_STP_CLK |= STR_STP_CLK_STOP_CLK;
u16 reg;
if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)) {
reg = readw(host->base + MMC_REG_STR_STP_CLK);
writew(reg & ~STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
while (i < 0x1000) {
if (!(i & 0x7f)) {
reg = readw(host->base + MMC_REG_STR_STP_CLK);
writew(reg | STR_STP_CLK_STOP_CLK,
host->base + MMC_REG_STR_STP_CLK);
}
reg = readw(host->base + MMC_REG_STATUS);
if (!(reg & STATUS_CARD_BUS_CLK_RUN)) {
/* Check twice before cut */
if(!(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN))
reg = readw(host->base + MMC_REG_STATUS);
if (!(reg & STATUS_CARD_BUS_CLK_RUN))
return;
}
@ -135,8 +128,10 @@ static int imxmci_start_clock(struct imxmci_host *host)
unsigned int trials = 0;
unsigned int delay_limit = 128;
unsigned long flags;
u16 reg;
MMC_STR_STP_CLK &= ~STR_STP_CLK_STOP_CLK;
reg = readw(host->base + MMC_REG_STR_STP_CLK);
writew(reg & ~STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
clear_bit(IMXMCI_PEND_STARTED_b, &host->pending_events);
@ -145,18 +140,21 @@ static int imxmci_start_clock(struct imxmci_host *host)
* then 6 delay loops, but during card detection (low clockrate)
* it takes up to 5000 delay loops and sometimes fails for the first time
*/
MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
reg = readw(host->base + MMC_REG_STR_STP_CLK);
writew(reg | STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
do {
unsigned int delay = delay_limit;
while(delay--){
if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
while (delay--) {
reg = readw(host->base + MMC_REG_STATUS);
if (reg & STATUS_CARD_BUS_CLK_RUN)
/* Check twice before cut */
if(MMC_STATUS & STATUS_CARD_BUS_CLK_RUN)
reg = readw(host->base + MMC_REG_STATUS);
if (reg & STATUS_CARD_BUS_CLK_RUN)
return 0;
if(test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
return 0;
}
@ -167,58 +165,59 @@ static int imxmci_start_clock(struct imxmci_host *host)
* IRQ or schedule delays this function execution and the clocks has
* been already stopped by other means (response processing, SDHC HW)
*/
if(!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events))
MMC_STR_STP_CLK |= STR_STP_CLK_START_CLK;
if (!test_bit(IMXMCI_PEND_STARTED_b, &host->pending_events)) {
reg = readw(host->base + MMC_REG_STR_STP_CLK);
writew(reg | STR_STP_CLK_START_CLK,
host->base + MMC_REG_STR_STP_CLK);
}
local_irq_restore(flags);
} while(++trials<256);
} while (++trials < 256);
dev_err(mmc_dev(host->mmc), "imxmci_start_clock blocked, no luck\n");
return -1;
}
static void imxmci_softreset(void)
static void imxmci_softreset(struct imxmci_host *host)
{
/* reset sequence */
MMC_STR_STP_CLK = 0x8;
MMC_STR_STP_CLK = 0xD;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
MMC_STR_STP_CLK = 0x5;
int i;
MMC_RES_TO = 0xff;
MMC_BLK_LEN = 512;
MMC_NOB = 1;
/* reset sequence */
writew(0x08, host->base + MMC_REG_STR_STP_CLK);
writew(0x0D, host->base + MMC_REG_STR_STP_CLK);
for (i = 0; i < 8; i++)
writew(0x05, host->base + MMC_REG_STR_STP_CLK);
writew(0xff, host->base + MMC_REG_RES_TO);
writew(512, host->base + MMC_REG_BLK_LEN);
writew(1, host->base + MMC_REG_NOB);
}
static int imxmci_busy_wait_for_status(struct imxmci_host *host,
unsigned int *pstat, unsigned int stat_mask,
int timeout, const char *where)
unsigned int *pstat, unsigned int stat_mask,
int timeout, const char *where)
{
int loops=0;
while(!(*pstat & stat_mask)) {
loops+=2;
if(loops >= timeout) {
int loops = 0;
while (!(*pstat & stat_mask)) {
loops += 2;
if (loops >= timeout) {
dev_dbg(mmc_dev(host->mmc), "busy wait timeout in %s, STATUS = 0x%x (0x%x)\n",
where, *pstat, stat_mask);
return -1;
}
udelay(2);
*pstat |= MMC_STATUS;
*pstat |= readw(host->base + MMC_REG_STATUS);
}
if(!loops)
if (!loops)
return 0;
/* The busy-wait is expected there for clock <8MHz due to SDHC hardware flaws */
if(!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock>=8000000))
if (!(stat_mask & STATUS_END_CMD_RESP) || (host->mmc->ios.clock >= 8000000))
dev_info(mmc_dev(host->mmc), "busy wait for %d usec in %s, STATUS = 0x%x (0x%x)\n",
loops, where, *pstat, stat_mask);
loops, where, *pstat, stat_mask);
return loops;
}
@ -235,8 +234,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
host->data = data;
data->bytes_xfered = 0;
MMC_NOB = nob;
MMC_BLK_LEN = blksz;
writew(nob, host->base + MMC_REG_NOB);
writew(blksz, host->base + MMC_REG_BLK_LEN);
/*
* DMA cannot be used for small block sizes, we have to use CPU driven transfers otherwise.
@ -252,14 +251,14 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
host->dma_dir = DMA_FROM_DEVICE;
/* Hack to enable read SCR */
MMC_NOB = 1;
MMC_BLK_LEN = 512;
writew(1, host->base + MMC_REG_NOB);
writew(512, host->base + MMC_REG_BLK_LEN);
} else {
host->dma_dir = DMA_TO_DEVICE;
}
/* Convert back to virtual address */
host->data_ptr = (u16*)sg_virt(data->sg);
host->data_ptr = (u16 *)sg_virt(data->sg);
host->data_cnt = 0;
clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events);
@ -271,10 +270,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
if (data->flags & MMC_DATA_READ) {
host->dma_dir = DMA_FROM_DEVICE;
host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
data->sg_len, host->dma_dir);
data->sg_len, host->dma_dir);
imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_READ);
host->res->start + MMC_REG_BUFFER_ACCESS,
DMA_MODE_READ);
/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_READ, IMX_DMA_WIDTH_16, CCR_REN);*/
CCR(host->dma) = CCR_DMOD_LINEAR | CCR_DSIZ_32 | CCR_SMOD_FIFO | CCR_SSIZ_16 | CCR_REN;
@ -282,10 +282,11 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
host->dma_dir = DMA_TO_DEVICE;
host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg,
data->sg_len, host->dma_dir);
data->sg_len, host->dma_dir);
imx_dma_setup_sg(host->dma, data->sg, data->sg_len, datasz,
host->res->start + MMC_BUFFER_ACCESS_OFS, DMA_MODE_WRITE);
host->res->start + MMC_REG_BUFFER_ACCESS,
DMA_MODE_WRITE);
/*imx_dma_setup_mem2dev_ccr(host->dma, DMA_MODE_WRITE, IMX_DMA_WIDTH_16, CCR_REN);*/
CCR(host->dma) = CCR_SMOD_LINEAR | CCR_SSIZ_32 | CCR_DMOD_FIFO | CCR_DSIZ_16 | CCR_REN;
@ -293,12 +294,12 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
#if 1 /* This code is there only for consistency checking and can be disabled in future */
host->dma_size = 0;
for(i=0; i<host->dma_nents; i++)
host->dma_size+=data->sg[i].length;
for (i = 0; i < host->dma_nents; i++)
host->dma_size += data->sg[i].length;
if (datasz > host->dma_size) {
dev_err(mmc_dev(host->mmc), "imxmci_setup_data datasz 0x%x > 0x%x dm_size\n",
datasz, host->dma_size);
datasz, host->dma_size);
}
#endif
@ -306,7 +307,7 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
wmb();
if(host->actual_bus_width == MMC_BUS_WIDTH_4)
if (host->actual_bus_width == MMC_BUS_WIDTH_4)
BLR(host->dma) = 0; /* burst 64 byte read / 64 bytes write */
else
BLR(host->dma) = 16; /* burst 16 byte read / 16 bytes write */
@ -317,9 +318,8 @@ static void imxmci_setup_data(struct imxmci_host *host, struct mmc_data *data)
clear_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events);
/* start DMA engine for read, write is delayed after initial response */
if (host->dma_dir == DMA_FROM_DEVICE) {
if (host->dma_dir == DMA_FROM_DEVICE)
imx_dma_enable(host->dma);
}
}
static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd, unsigned int cmdat)
@ -351,16 +351,16 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
break;
}
if ( test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events) )
if (test_and_clear_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events))
cmdat |= CMD_DAT_CONT_INIT; /* This command needs init */
if ( host->actual_bus_width == MMC_BUS_WIDTH_4 )
if (host->actual_bus_width == MMC_BUS_WIDTH_4)
cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
MMC_CMD = cmd->opcode;
MMC_ARGH = cmd->arg >> 16;
MMC_ARGL = cmd->arg & 0xffff;
MMC_CMD_DAT_CONT = cmdat;
writew(cmd->opcode, host->base + MMC_REG_CMD);
writew(cmd->arg >> 16, host->base + MMC_REG_ARGH);
writew(cmd->arg & 0xffff, host->base + MMC_REG_ARGL);
writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
atomic_set(&host->stuck_timeout, 0);
set_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events);
@ -368,18 +368,18 @@ static void imxmci_start_cmd(struct imxmci_host *host, struct mmc_command *cmd,
imask = IMXMCI_INT_MASK_DEFAULT;
imask &= ~INT_MASK_END_CMD_RES;
if ( cmdat & CMD_DAT_CONT_DATA_ENABLE ) {
/*imask &= ~INT_MASK_BUF_READY;*/
if (cmdat & CMD_DAT_CONT_DATA_ENABLE) {
/* imask &= ~INT_MASK_BUF_READY; */
imask &= ~INT_MASK_DATA_TRAN;
if ( cmdat & CMD_DAT_CONT_WRITE )
if (cmdat & CMD_DAT_CONT_WRITE)
imask &= ~INT_MASK_WRITE_OP_DONE;
if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
imask &= ~INT_MASK_BUF_READY;
}
spin_lock_irqsave(&host->lock, flags);
host->imask = imask;
MMC_INT_MASK = host->imask;
writew(host->imask, host->base + MMC_REG_INT_MASK);
spin_unlock_irqrestore(&host->lock, flags);
dev_dbg(mmc_dev(host->mmc), "CMD%02d (0x%02x) mask set to 0x%04x\n",
@ -395,14 +395,14 @@ static void imxmci_finish_request(struct imxmci_host *host, struct mmc_request *
spin_lock_irqsave(&host->lock, flags);
host->pending_events &= ~(IMXMCI_PEND_WAIT_RESP_m | IMXMCI_PEND_DMA_END_m |
IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
IMXMCI_PEND_DMA_DATA_m | IMXMCI_PEND_CPU_DATA_m);
host->imask = IMXMCI_INT_MASK_DEFAULT;
MMC_INT_MASK = host->imask;
writew(host->imask, host->base + MMC_REG_INT_MASK);
spin_unlock_irqrestore(&host->lock, flags);
if(req && req->cmd)
if (req && req->cmd)
host->prev_cmd_code = req->cmd->opcode;
host->req = NULL;
@ -416,17 +416,17 @@ static int imxmci_finish_data(struct imxmci_host *host, unsigned int stat)
struct mmc_data *data = host->data;
int data_error;
if(test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)){
if (test_and_clear_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
imx_dma_disable(host->dma);
dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents,
host->dma_dir);
}
if ( stat & STATUS_ERR_MASK ) {
dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",stat);
if(stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
if (stat & STATUS_ERR_MASK) {
dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", stat);
if (stat & (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR))
data->error = -EILSEQ;
else if(stat & STATUS_TIME_OUT_READ)
else if (stat & STATUS_TIME_OUT_READ)
data->error = -ETIMEDOUT;
else
data->error = -EIO;
@ -445,7 +445,7 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
{
struct mmc_command *cmd = host->cmd;
int i;
u32 a,b,c;
u32 a, b, c;
struct mmc_data *data = host->data;
if (!cmd)
@ -461,18 +461,18 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
cmd->error = -EILSEQ;
}
if(cmd->flags & MMC_RSP_PRESENT) {
if(cmd->flags & MMC_RSP_136) {
if (cmd->flags & MMC_RSP_PRESENT) {
if (cmd->flags & MMC_RSP_136) {
for (i = 0; i < 4; i++) {
u32 a = MMC_RES_FIFO & 0xffff;
u32 b = MMC_RES_FIFO & 0xffff;
cmd->resp[i] = a<<16 | b;
a = readw(host->base + MMC_REG_RES_FIFO);
b = readw(host->base + MMC_REG_RES_FIFO);
cmd->resp[i] = a << 16 | b;
}
} else {
a = MMC_RES_FIFO & 0xffff;
b = MMC_RES_FIFO & 0xffff;
c = MMC_RES_FIFO & 0xffff;
cmd->resp[0] = a<<24 | b<<8 | c>>8;
a = readw(host->base + MMC_REG_RES_FIFO);
b = readw(host->base + MMC_REG_RES_FIFO);
c = readw(host->base + MMC_REG_RES_FIFO);
cmd->resp[0] = a << 24 | b << 8 | c >> 8;
}
}
@ -484,36 +484,34 @@ static int imxmci_cmd_done(struct imxmci_host *host, unsigned int stat)
/* Wait for FIFO to be empty before starting DMA write */
stat = MMC_STATUS;
if(imxmci_busy_wait_for_status(host, &stat,
STATUS_APPL_BUFF_FE,
40, "imxmci_cmd_done DMA WR") < 0) {
stat = readw(host->base + MMC_REG_STATUS);
if (imxmci_busy_wait_for_status(host, &stat,
STATUS_APPL_BUFF_FE,
40, "imxmci_cmd_done DMA WR") < 0) {
cmd->error = -EIO;
imxmci_finish_data(host, stat);
if(host->req)
if (host->req)
imxmci_finish_request(host, host->req);
dev_warn(mmc_dev(host->mmc), "STATUS = 0x%04x\n",
stat);
stat);
return 0;
}
if(test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
imx_dma_enable(host->dma);
}
}
} else {
struct mmc_request *req;
imxmci_stop_clock(host);
req = host->req;
if(data)
if (data)
imxmci_finish_data(host, stat);
if( req ) {
if (req)
imxmci_finish_request(host, req);
} else {
else
dev_warn(mmc_dev(host->mmc), "imxmci_cmd_done: no request to finish\n");
}
}
return 1;
@ -535,11 +533,10 @@ static int imxmci_data_done(struct imxmci_host *host, unsigned int stat)
} else {
struct mmc_request *req;
req = host->req;
if( req ) {
if (req)
imxmci_finish_request(host, req);
} else {
else
dev_warn(mmc_dev(host->mmc), "imxmci_data_done: no request to finish\n");
}
}
return 1;
@ -552,7 +549,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
int trans_done = 0;
unsigned int stat = *pstat;
if(host->actual_bus_width != MMC_BUS_WIDTH_4)
if (host->actual_bus_width != MMC_BUS_WIDTH_4)
burst_len = 16;
else
burst_len = 64;
@ -563,44 +560,44 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
udelay(20); /* required for clocks < 8MHz*/
if(host->dma_dir == DMA_FROM_DEVICE) {
if (host->dma_dir == DMA_FROM_DEVICE) {
imxmci_busy_wait_for_status(host, &stat,
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
STATUS_TIME_OUT_READ,
50, "imxmci_cpu_driven_data read");
STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE |
STATUS_TIME_OUT_READ,
50, "imxmci_cpu_driven_data read");
while((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
!(stat & STATUS_TIME_OUT_READ) &&
(host->data_cnt < 512)) {
while ((stat & (STATUS_APPL_BUFF_FF | STATUS_DATA_TRANS_DONE)) &&
!(stat & STATUS_TIME_OUT_READ) &&
(host->data_cnt < 512)) {
udelay(20); /* required for clocks < 8MHz*/
for(i = burst_len; i>=2 ; i-=2) {
for (i = burst_len; i >= 2 ; i -= 2) {
u16 data;
data = MMC_BUFFER_ACCESS;
data = readw(host->base + MMC_REG_BUFFER_ACCESS);
udelay(10); /* required for clocks < 8MHz*/
if(host->data_cnt+2 <= host->dma_size) {
if (host->data_cnt+2 <= host->dma_size) {
*(host->data_ptr++) = data;
} else {
if(host->data_cnt < host->dma_size)
*(u8*)(host->data_ptr) = data;
if (host->data_cnt < host->dma_size)
*(u8 *)(host->data_ptr) = data;
}
host->data_cnt += 2;
}
stat = MMC_STATUS;
stat = readw(host->base + MMC_REG_STATUS);
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read %d burst %d STATUS = 0x%x\n",
host->data_cnt, burst_len, stat);
}
if((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
if ((stat & STATUS_DATA_TRANS_DONE) && (host->data_cnt >= 512))
trans_done = 1;
if(host->dma_size & 0x1ff)
if (host->dma_size & 0x1ff)
stat &= ~STATUS_CRC_READ_ERR;
if(stat & STATUS_TIME_OUT_READ) {
if (stat & STATUS_TIME_OUT_READ) {
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data read timeout STATUS = 0x%x\n",
stat);
trans_done = -1;
@ -608,12 +605,12 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
} else {
imxmci_busy_wait_for_status(host, &stat,
STATUS_APPL_BUFF_FE,
20, "imxmci_cpu_driven_data write");
STATUS_APPL_BUFF_FE,
20, "imxmci_cpu_driven_data write");
while((stat & STATUS_APPL_BUFF_FE) &&
(host->data_cnt < host->dma_size)) {
if(burst_len >= host->dma_size - host->data_cnt) {
while ((stat & STATUS_APPL_BUFF_FE) &&
(host->data_cnt < host->dma_size)) {
if (burst_len >= host->dma_size - host->data_cnt) {
burst_len = host->dma_size - host->data_cnt;
host->data_cnt = host->dma_size;
trans_done = 1;
@ -621,10 +618,10 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
host->data_cnt += burst_len;
}
for(i = burst_len; i>0 ; i-=2)
MMC_BUFFER_ACCESS = *(host->data_ptr++);
for (i = burst_len; i > 0 ; i -= 2)
writew(*(host->data_ptr++), host->base + MMC_REG_BUFFER_ACCESS);
stat = MMC_STATUS;
stat = readw(host->base + MMC_REG_STATUS);
dev_dbg(mmc_dev(host->mmc), "imxmci_cpu_driven_data write burst %d STATUS = 0x%x\n",
burst_len, stat);
@ -639,7 +636,7 @@ static int imxmci_cpu_driven_data(struct imxmci_host *host, unsigned int *pstat)
static void imxmci_dma_irq(int dma, void *devid)
{
struct imxmci_host *host = devid;
uint32_t stat = MMC_STATUS;
u32 stat = readw(host->base + MMC_REG_STATUS);
atomic_set(&host->stuck_timeout, 0);
host->status_reg = stat;
@ -650,10 +647,11 @@ static void imxmci_dma_irq(int dma, void *devid)
static irqreturn_t imxmci_irq(int irq, void *devid)
{
struct imxmci_host *host = devid;
uint32_t stat = MMC_STATUS;
u32 stat = readw(host->base + MMC_REG_STATUS);
int handled = 1;
MMC_INT_MASK = host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT;
writew(host->imask | INT_MASK_SDIO | INT_MASK_AUTO_CARD_DETECT,
host->base + MMC_REG_INT_MASK);
atomic_set(&host->stuck_timeout, 0);
host->status_reg = stat;
@ -671,10 +669,10 @@ static void imxmci_tasklet_fnc(unsigned long data)
unsigned int data_dir_mask = 0; /* STATUS_WR_CRC_ERROR_CODE_MASK */
int timeout = 0;
if(atomic_read(&host->stuck_timeout) > 4) {
if (atomic_read(&host->stuck_timeout) > 4) {
char *what;
timeout = 1;
stat = MMC_STATUS;
stat = readw(host->base + MMC_REG_STATUS);
host->status_reg = stat;
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
@ -683,29 +681,37 @@ static void imxmci_tasklet_fnc(unsigned long data)
what = "RESP";
else
if (test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events))
if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events))
what = "DATA";
else
what = "DMA";
else
what = "???";
dev_err(mmc_dev(host->mmc), "%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
what, stat, MMC_INT_MASK);
dev_err(mmc_dev(host->mmc), "CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
MMC_CMD_DAT_CONT, MMC_BLK_LEN, MMC_NOB, CCR(host->dma));
dev_err(mmc_dev(host->mmc),
"%s TIMEOUT, hardware stucked STATUS = 0x%04x IMASK = 0x%04x\n",
what, stat,
readw(host->base + MMC_REG_INT_MASK));
dev_err(mmc_dev(host->mmc),
"CMD_DAT_CONT = 0x%04x, MMC_BLK_LEN = 0x%04x, MMC_NOB = 0x%04x, DMA_CCR = 0x%08x\n",
readw(host->base + MMC_REG_CMD_DAT_CONT),
readw(host->base + MMC_REG_BLK_LEN),
readw(host->base + MMC_REG_NOB),
CCR(host->dma));
dev_err(mmc_dev(host->mmc), "CMD%d, prevCMD%d, bus %d-bit, dma_size = 0x%x\n",
host->cmd?host->cmd->opcode:0, host->prev_cmd_code, 1<<host->actual_bus_width, host->dma_size);
host->cmd ? host->cmd->opcode : 0,
host->prev_cmd_code,
1 << host->actual_bus_width, host->dma_size);
}
if(!host->present || timeout)
if (!host->present || timeout)
host->status_reg = STATUS_TIME_OUT_RESP | STATUS_TIME_OUT_READ |
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR;
if(test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
if (test_bit(IMXMCI_PEND_IRQ_b, &host->pending_events) || timeout) {
clear_bit(IMXMCI_PEND_IRQ_b, &host->pending_events);
stat = MMC_STATUS;
stat = readw(host->base + MMC_REG_STATUS);
/*
* This is not required in theory, but there is chance to miss some flag
* which clears automatically by mask write, FreeScale original code keeps
@ -713,63 +719,62 @@ static void imxmci_tasklet_fnc(unsigned long data)
*/
stat |= host->status_reg;
if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events))
stat &= ~STATUS_CRC_READ_ERR;
if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
imxmci_busy_wait_for_status(host, &stat,
STATUS_END_CMD_RESP | STATUS_ERR_MASK,
20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
STATUS_END_CMD_RESP | STATUS_ERR_MASK,
20, "imxmci_tasklet_fnc resp (ERRATUM #4)");
}
if(stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
if (stat & (STATUS_END_CMD_RESP | STATUS_ERR_MASK)) {
if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
imxmci_cmd_done(host, stat);
if(host->data && (stat & STATUS_ERR_MASK))
if (host->data && (stat & STATUS_ERR_MASK))
imxmci_data_done(host, stat);
}
if(test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
stat |= MMC_STATUS;
if(imxmci_cpu_driven_data(host, &stat)){
if(test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
if (test_bit(IMXMCI_PEND_CPU_DATA_b, &host->pending_events)) {
stat |= readw(host->base + MMC_REG_STATUS);
if (imxmci_cpu_driven_data(host, &stat)) {
if (test_and_clear_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events))
imxmci_cmd_done(host, stat);
atomic_clear_mask(IMXMCI_PEND_IRQ_m|IMXMCI_PEND_CPU_DATA_m,
&host->pending_events);
&host->pending_events);
imxmci_data_done(host, stat);
}
}
}
if(test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
!test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
if (test_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events) &&
!test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events)) {
stat = MMC_STATUS;
stat = readw(host->base + MMC_REG_STATUS);
/* Same as above */
stat |= host->status_reg;
if(host->dma_dir == DMA_TO_DEVICE) {
if (host->dma_dir == DMA_TO_DEVICE)
data_dir_mask = STATUS_WRITE_OP_DONE;
} else {
else
data_dir_mask = STATUS_DATA_TRANS_DONE;
}
if(stat & data_dir_mask) {
if (stat & data_dir_mask) {
clear_bit(IMXMCI_PEND_DMA_END_b, &host->pending_events);
imxmci_data_done(host, stat);
}
}
if(test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
if (test_and_clear_bit(IMXMCI_PEND_CARD_XCHG_b, &host->pending_events)) {
if(host->cmd)
if (host->cmd)
imxmci_cmd_done(host, STATUS_TIME_OUT_RESP);
if(host->data)
if (host->data)
imxmci_data_done(host, STATUS_TIME_OUT_READ |
STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR);
if(host->req)
if (host->req)
imxmci_finish_request(host, host->req);
mmc_detect_change(host->mmc, msecs_to_jiffies(100));
@ -796,9 +801,8 @@ static void imxmci_request(struct mmc_host *mmc, struct mmc_request *req)
if (req->data->flags & MMC_DATA_WRITE)
cmdat |= CMD_DAT_CONT_WRITE;
if (req->data->flags & MMC_DATA_STREAM) {
if (req->data->flags & MMC_DATA_STREAM)
cmdat |= CMD_DAT_CONT_STREAM_BLOCK;
}
}
imxmci_start_cmd(host, req->cmd, cmdat);
@ -811,36 +815,37 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
struct imxmci_host *host = mmc_priv(mmc);
int prescaler;
if( ios->bus_width==MMC_BUS_WIDTH_4 ) {
if (ios->bus_width == MMC_BUS_WIDTH_4) {
host->actual_bus_width = MMC_BUS_WIDTH_4;
imx_gpio_mode(PB11_PF_SD_DAT3);
}else{
} else {
host->actual_bus_width = MMC_BUS_WIDTH_1;
imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | 11);
}
if ( host->power_mode != ios->power_mode ) {
if (host->power_mode != ios->power_mode) {
switch (ios->power_mode) {
case MMC_POWER_OFF:
break;
break;
case MMC_POWER_UP:
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
break;
break;
case MMC_POWER_ON:
break;
break;
}
host->power_mode = ios->power_mode;
}
if ( ios->clock ) {
if (ios->clock) {
unsigned int clk;
u16 reg;
/* The prescaler is 5 for PERCLK2 equal to 96MHz
* then 96MHz / 5 = 19.2 MHz
*/
clk = clk_get_rate(host->clk);
prescaler=(clk+(CLK_RATE*7)/8)/CLK_RATE;
switch(prescaler) {
prescaler = (clk + (CLK_RATE * 7) / 8) / CLK_RATE;
switch (prescaler) {
case 0:
case 1: prescaler = 0;
break;
@ -858,24 +863,29 @@ static void imxmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
dev_dbg(mmc_dev(host->mmc), "PERCLK2 %d MHz -> prescaler %d\n",
clk, prescaler);
for(clk=0; clk<8; clk++) {
for (clk = 0; clk < 8; clk++) {
int x;
x = CLK_RATE / (1<<clk);
if( x <= ios->clock)
x = CLK_RATE / (1 << clk);
if (x <= ios->clock)
break;
}
MMC_STR_STP_CLK |= STR_STP_CLK_ENABLE; /* enable controller */
/* enable controller */
reg = readw(host->base + MMC_REG_STR_STP_CLK);
writew(reg | STR_STP_CLK_ENABLE,
host->base + MMC_REG_STR_STP_CLK);
imxmci_stop_clock(host);
MMC_CLK_RATE = (prescaler<<3) | clk;
writew((prescaler << 3) | clk, host->base + MMC_REG_CLK_RATE);
/*
* Under my understanding, clock should not be started there, because it would
* initiate SDHC sequencer and send last or random command into card
*/
/*imxmci_start_clock(host);*/
/* imxmci_start_clock(host); */
dev_dbg(mmc_dev(host->mmc), "MMC_CLK_RATE: 0x%08x\n", MMC_CLK_RATE);
dev_dbg(mmc_dev(host->mmc),
"MMC_CLK_RATE: 0x%08x\n",
readw(host->base + MMC_REG_CLK_RATE));
} else {
imxmci_stop_clock(host);
}
@ -915,10 +925,10 @@ static void imxmci_check_status(unsigned long data)
tasklet_schedule(&host->tasklet);
}
if(test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
if (test_bit(IMXMCI_PEND_WAIT_RESP_b, &host->pending_events) ||
test_bit(IMXMCI_PEND_DMA_DATA_b, &host->pending_events)) {
atomic_inc(&host->stuck_timeout);
if(atomic_read(&host->stuck_timeout) > 4)
if (atomic_read(&host->stuck_timeout) > 4)
tasklet_schedule(&host->tasklet);
} else {
atomic_set(&host->stuck_timeout, 0);
@ -934,6 +944,7 @@ static int imxmci_probe(struct platform_device *pdev)
struct imxmci_host *host = NULL;
struct resource *r;
int ret = 0, irq;
u16 rev_no;
printk(KERN_INFO "i.MX mmc driver\n");
@ -942,7 +953,8 @@ static int imxmci_probe(struct platform_device *pdev)
if (!r || irq < 0)
return -ENXIO;
if (!request_mem_region(r->start, 0x100, pdev->name))
r = request_mem_region(r->start, resource_size(r), pdev->name);
if (!r)
return -EBUSY;
mmc = mmc_alloc_host(sizeof(struct imxmci_host), &pdev->dev);
@ -966,6 +978,12 @@ static int imxmci_probe(struct platform_device *pdev)
mmc->max_blk_count = 65535;
host = mmc_priv(mmc);
host->base = ioremap(r->start, resource_size(r));
if (!host->base) {
ret = -ENOMEM;
goto out;
}
host->mmc = mmc;
host->dma_allocated = 0;
host->pdata = pdev->dev.platform_data;
@ -993,18 +1011,20 @@ static int imxmci_probe(struct platform_device *pdev)
imx_gpio_mode(PB12_PF_SD_CLK);
imx_gpio_mode(PB13_PF_SD_CMD);
imxmci_softreset();
imxmci_softreset(host);
if ( MMC_REV_NO != 0x390 ) {
rev_no = readw(host->base + MMC_REG_REV_NO);
if (rev_no != 0x390) {
dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
MMC_REV_NO);
readw(host->base + MMC_REG_REV_NO));
goto out;
}
MMC_READ_TO = 0x2db4; /* recommended in data sheet */
/* recommended in data sheet */
writew(0x2db4, host->base + MMC_REG_READ_TO);
host->imask = IMXMCI_INT_MASK_DEFAULT;
MMC_INT_MASK = host->imask;
writew(host->imask, host->base + MMC_REG_INT_MASK);
host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW);
if(host->dma < 0) {
@ -1012,7 +1032,7 @@ static int imxmci_probe(struct platform_device *pdev)
ret = -EBUSY;
goto out;
}
host->dma_allocated=1;
host->dma_allocated = 1;
imx_dma_setup_handlers(host->dma, imxmci_dma_irq, NULL, host);
tasklet_init(&host->tasklet, imxmci_tasklet_fnc, (unsigned long)host);
@ -1032,7 +1052,7 @@ static int imxmci_probe(struct platform_device *pdev)
host->timer.data = (unsigned long)host;
host->timer.function = imxmci_check_status;
add_timer(&host->timer);
mod_timer(&host->timer, jiffies + (HZ>>1));
mod_timer(&host->timer, jiffies + (HZ >> 1));
platform_set_drvdata(pdev, mmc);
@ -1042,18 +1062,20 @@ static int imxmci_probe(struct platform_device *pdev)
out:
if (host) {
if(host->dma_allocated){
if (host->dma_allocated) {
imx_dma_free(host->dma);
host->dma_allocated=0;
host->dma_allocated = 0;
}
if (host->clk) {
clk_disable(host->clk);
clk_put(host->clk);
}
if (host->base)
iounmap(host->base);
}
if (mmc)
mmc_free_host(mmc);
release_mem_region(r->start, 0x100);
release_mem_region(r->start, resource_size(r));
return ret;
}
@ -1072,9 +1094,10 @@ static int imxmci_remove(struct platform_device *pdev)
mmc_remove_host(mmc);
free_irq(host->irq, host);
if(host->dma_allocated){
iounmap(host->base);
if (host->dma_allocated) {
imx_dma_free(host->dma);
host->dma_allocated=0;
host->dma_allocated = 0;
}
tasklet_kill(&host->tasklet);
@ -1082,7 +1105,7 @@ static int imxmci_remove(struct platform_device *pdev)
clk_disable(host->clk);
clk_put(host->clk);
release_mem_region(host->res->start, 0x100);
release_mem_region(host->res->start, resource_size(host->res));
mmc_free_host(mmc);
}
@ -1109,7 +1132,7 @@ static int imxmci_resume(struct platform_device *dev)
if (mmc) {
host = mmc_priv(mmc);
if(host)
if (host)
set_bit(IMXMCI_PEND_SET_INIT_b, &host->pending_events);
ret = mmc_resume_host(mmc);
}

37
drivers/mmc/host/imxmmc.h
View File

@ -1,24 +1,21 @@
#define MMC_REG_STR_STP_CLK 0x00
#define MMC_REG_STATUS 0x04
#define MMC_REG_CLK_RATE 0x08
#define MMC_REG_CMD_DAT_CONT 0x0C
#define MMC_REG_RES_TO 0x10
#define MMC_REG_READ_TO 0x14
#define MMC_REG_BLK_LEN 0x18
#define MMC_REG_NOB 0x1C
#define MMC_REG_REV_NO 0x20
#define MMC_REG_INT_MASK 0x24
#define MMC_REG_CMD 0x28
#define MMC_REG_ARGH 0x2C
#define MMC_REG_ARGL 0x30
#define MMC_REG_RES_FIFO 0x34
#define MMC_REG_BUFFER_ACCESS 0x38
# define __REG16(x) (*((volatile u16 *)IO_ADDRESS(x)))
#define MMC_STR_STP_CLK __REG16(IMX_MMC_BASE + 0x00)
#define MMC_STATUS __REG16(IMX_MMC_BASE + 0x04)
#define MMC_CLK_RATE __REG16(IMX_MMC_BASE + 0x08)
#define MMC_CMD_DAT_CONT __REG16(IMX_MMC_BASE + 0x0C)
#define MMC_RES_TO __REG16(IMX_MMC_BASE + 0x10)
#define MMC_READ_TO __REG16(IMX_MMC_BASE + 0x14)
#define MMC_BLK_LEN __REG16(IMX_MMC_BASE + 0x18)
#define MMC_NOB __REG16(IMX_MMC_BASE + 0x1C)
#define MMC_REV_NO __REG16(IMX_MMC_BASE + 0x20)
#define MMC_INT_MASK __REG16(IMX_MMC_BASE + 0x24)
#define MMC_CMD __REG16(IMX_MMC_BASE + 0x28)
#define MMC_ARGH __REG16(IMX_MMC_BASE + 0x2C)
#define MMC_ARGL __REG16(IMX_MMC_BASE + 0x30)
#define MMC_RES_FIFO __REG16(IMX_MMC_BASE + 0x34)
#define MMC_BUFFER_ACCESS __REG16(IMX_MMC_BASE + 0x38)
#define MMC_BUFFER_ACCESS_OFS 0x38
#define STR_STP_CLK_IPG_CLK_GATE_DIS (1<<15)
#define STR_STP_CLK_IPG_PERCLK_GATE_DIS (1<<14)
#define STR_STP_CLK_ENDIAN (1<<5)
#define STR_STP_CLK_RESET (1<<3)
#define STR_STP_CLK_ENABLE (1<<2)

2
drivers/mtd/nand/Kconfig
View File

@ -408,7 +408,7 @@ config MTD_NAND_FSL_UPM
config MTD_NAND_MXC
tristate "MXC NAND support"
depends on ARCH_MX2
depends on ARCH_MX2 || ARCH_MX3
help
This enables the driver for the NAND flash controller on the
MXC processors.

6
drivers/serial/imx.c
View File

@ -66,7 +66,7 @@
#define ONEMS 0xb0 /* One Millisecond register */
#define UTS 0xb4 /* UART Test Register */
#endif
#ifdef CONFIG_ARCH_IMX
#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
#define BIPR1 0xb0 /* Incremental Preset Register 1 */
#define BIPR2 0xb4 /* Incremental Preset Register 2 */
#define BIPR3 0xb8 /* Incremental Preset Register 3 */
@ -96,7 +96,7 @@
#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
#define UCR1_SNDBRK (1<<4) /* Send break */
#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
#ifdef CONFIG_ARCH_IMX
#if defined(CONFIG_ARCH_IMX) || defined(CONFIG_ARCH_MX1)
#define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */
#endif
#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
@ -187,7 +187,7 @@
#define MAX_INTERNAL_IRQ IMX_IRQS
#endif
#if defined CONFIG_ARCH_MX3 || defined CONFIG_ARCH_MX2
#ifdef CONFIG_ARCH_MXC
#define SERIAL_IMX_MAJOR 207
#define MINOR_START 16
#define DEV_NAME "ttymxc"