OMAP3 clock: add a short delay when lowering CORE clk rate
When changing the SDRAM clock from 166MHz to 83MHz via the CORE DPLL M2 divider, add a short delay before returning to SDRAM to allow the SDRC time to stabilize. Without this delay, the system is prone to random panics upon re-entering SDRAM. This time delay varies based on MPU frequency. At 500MHz MPU frequency at room temperature, 64 loops seems to work okay; so add another 32 loops for environmental and process variation. Signed-off-by: Paul Walmsley <paul@pwsan.com>
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c9812d042a
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@ -286,6 +286,20 @@ static struct omap_clk omap34xx_clks[] = {
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#define MIN_SDRC_DLL_LOCK_FREQ 83000000
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#define CYCLES_PER_MHZ 1000000
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/* Scale factor for fixed-point arith in omap3_core_dpll_m2_set_rate() */
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#define SDRC_MPURATE_SCALE 8
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/* 2^SDRC_MPURATE_BASE_SHIFT: MPU MHz that SDRC_MPURATE_LOOPS is defined for */
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#define SDRC_MPURATE_BASE_SHIFT 9
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/*
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* SDRC_MPURATE_LOOPS: Number of MPU loops to execute at
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* 2^MPURATE_BASE_SHIFT MHz for SDRC to stabilize
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*/
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#define SDRC_MPURATE_LOOPS 96
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/**
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* omap3_dpll_recalc - recalculate DPLL rate
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* @clk: DPLL struct clk
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@ -709,7 +723,8 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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{
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u32 new_div = 0;
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u32 unlock_dll = 0;
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unsigned long validrate, sdrcrate;
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u32 c;
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unsigned long validrate, sdrcrate, mpurate;
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struct omap_sdrc_params *sp;
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if (!clk || !rate)
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@ -737,6 +752,17 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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unlock_dll = 1;
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}
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/*
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* XXX This only needs to be done when the CPU frequency changes
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*/
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mpurate = arm_fck.rate / CYCLES_PER_MHZ;
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c = (mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
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c += 1; /* for safety */
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c *= SDRC_MPURATE_LOOPS;
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c >>= SDRC_MPURATE_SCALE;
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if (c == 0)
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c = 1;
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pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
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validrate);
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pr_debug("clock: SDRC timing params used: %08x %08x %08x\n",
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@ -747,7 +773,7 @@ static int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
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/* REVISIT: Add SDRC_MR changing to this code also */
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omap3_configure_core_dpll(sp->rfr_ctrl, sp->actim_ctrla,
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sp->actim_ctrlb, new_div, unlock_dll);
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sp->actim_ctrlb, new_div, unlock_dll, c);
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return 0;
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}
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@ -42,10 +42,14 @@
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* r0 = sdrc_rfr_ctrl r1 = sdrc_actim_ctrla r2 = sdrc_actim_ctrlb r3 = M2
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* r4 = Unlock SDRC DLL? (1 = yes, 0 = no) -- only unlock DLL for
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* SDRC rates < 83MHz
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* r5 = number of MPU cycles to wait for SDRC to stabilize after
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* reprogramming the SDRC when switching to a slower MPU speed
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*
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*/
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ENTRY(omap3_sram_configure_core_dpll)
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stmfd sp!, {r1-r12, lr} @ store regs to stack
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ldr r4, [sp, #52] @ pull extra args off the stack
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ldr r5, [sp, #56] @ load extra args from the stack
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dsb @ flush buffered writes to interconnect
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cmp r3, #0x2
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blne configure_sdrc
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@ -59,7 +63,11 @@ ENTRY(omap3_sram_configure_core_dpll)
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bleq wait_dll_unlock
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blne wait_dll_lock
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cmp r3, #0x1
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blne configure_sdrc
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beq return_to_sdram
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bl configure_sdrc
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mov r12, r5 @ if slowing, wait for SDRC to stabilize
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bl wait_clk_stable
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return_to_sdram:
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isb @ prevent speculative exec past here
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mov r0, #0 @ return value
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ldmfd sp!, {r1-r12, pc} @ restore regs and return
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@ -106,16 +114,6 @@ configure_core_dpll:
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wait_clk_stable:
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subs r12, r12, #1
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bne wait_clk_stable
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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bx lr
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enable_sdrc:
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ldr r11, omap3_cm_iclken1_core
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@ -24,7 +24,7 @@ extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll);
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u32 unlock_dll, u32 f);
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/* Do not use these */
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extern void omap1_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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@ -62,7 +62,7 @@ extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2,
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u32 unlock_dll);
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u32 unlock_dll, u32 f);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
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#endif
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@ -371,15 +371,17 @@ static inline int omap243x_sram_init(void)
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static u32 (*_omap3_sram_configure_core_dpll)(u32 sdrc_rfr_ctrl,
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u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb,
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u32 m2, u32 unlock_dll);
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u32 m2, u32 unlock_dll,
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u32 f);
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u32 omap3_configure_core_dpll(u32 sdrc_rfr_ctrl, u32 sdrc_actim_ctrla,
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u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll)
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u32 sdrc_actim_ctrlb, u32 m2, u32 unlock_dll,
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u32 f)
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{
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BUG_ON(!_omap3_sram_configure_core_dpll);
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return _omap3_sram_configure_core_dpll(sdrc_rfr_ctrl,
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sdrc_actim_ctrla,
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sdrc_actim_ctrlb, m2,
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unlock_dll);
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unlock_dll, f);
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}
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/* REVISIT: Should this be same as omap34xx_sram_init() after off-idle? */
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