MIPS: Octeon: Apply CN63XXP1 errata workarounds.
The CN63XXP1 needs a couple of workarounds to ensure memory is not written in unexpected ways. All PREF with hints in the range 0-4,6-24 are replaced with PREF 28. We pass a flag to the assembler to cover compiler generated code, and patch uasm for the dynamically generated code. The write buffer threshold is reduced to 4. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1672/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>hifive-unleashed-5.1
David Daney
Ralf Baechle
parent
468ffde46d
commit
c9941158fd
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@ -156,6 +156,7 @@ cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap
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ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON))))
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cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += -Wa,-march=octeon
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endif
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cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1
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cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,)
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cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,)
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@ -3,6 +3,17 @@ config CAVIUM_OCTEON_SPECIFIC_OPTIONS
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depends on CPU_CAVIUM_OCTEON
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default "y"
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config CAVIUM_CN63XXP1
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bool "Enable CN63XXP1 errata worarounds"
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depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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default "n"
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help
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The CN63XXP1 chip requires build time workarounds to
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function reliably, select this option to enable them. These
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workarounds will cause a slight decrease in performance on
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non-CN63XXP1 hardware, so it is recommended to select "n"
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unless it is known the workarounds are needed.
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config CAVIUM_OCTEON_2ND_KERNEL
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bool "Build the kernel to be used as a 2nd kernel on the same chip"
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depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS
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@ -356,8 +356,18 @@ void octeon_user_io_init(void)
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cvmmemctl.s.wbfltime = 0;
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/* R/W If set, do not put Istream in the L2 cache. */
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cvmmemctl.s.istrnol2 = 0;
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/* R/W The write buffer threshold. */
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cvmmemctl.s.wbthresh = 10;
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/*
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* R/W The write buffer threshold. As per erratum Core-14752
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* for CN63XX, a sc/scd might fail if the write buffer is
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* full. Lowering WBTHRESH greatly lowers the chances of the
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* write buffer ever being full and triggering the erratum.
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*/
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X))
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cvmmemctl.s.wbthresh = 4;
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else
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cvmmemctl.s.wbthresh = 10;
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/* R/W If set, CVMSEG is available for loads/stores in
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* kernel/debug mode. */
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#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
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@ -375,14 +385,13 @@ void octeon_user_io_init(void)
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* is max legal value. */
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cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE;
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write_c0_cvmmemctl(cvmmemctl.u64);
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if (smp_processor_id() == 0)
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pr_notice("CVMSEG size: %d cache lines (%d bytes)\n",
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE,
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CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128);
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write_c0_cvmmemctl(cvmmemctl.u64);
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/* Move the performance counter interrupts to IRQ 6 */
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cvmctl = read_c0_cvmctl();
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cvmctl &= ~(7 << 7);
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@ -758,6 +767,31 @@ EXPORT_SYMBOL(prom_putchar);
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void prom_free_prom_memory(void)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) {
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/* Check for presence of Core-14449 fix. */
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u32 insn;
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u32 *foo;
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foo = &insn;
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asm volatile("# before" : : : "memory");
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prefetch(foo);
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asm volatile(
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".set push\n\t"
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".set noreorder\n\t"
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"bal 1f\n\t"
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"nop\n"
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"1:\tlw %0,-12($31)\n\t"
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".set pop\n\t"
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: "=r" (insn) : : "$31", "memory");
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if ((insn >> 26) != 0x33)
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panic("No PREF instruction at Core-14449 probe point.\n");
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if (((insn >> 16) & 0x1f) != 28)
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panic("Core-14449 WAR not in place (%04x).\n"
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"Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1).\n", insn);
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}
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#ifdef CONFIG_CAVIUM_DECODE_RSL
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cvmx_interrupt_rsl_enable();
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@ -405,7 +405,6 @@ I_u1u2u3(_mfc0)
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I_u1u2u3(_mtc0)
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I_u2u1u3(_ori)
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I_u3u1u2(_or)
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I_u2s3u1(_pref)
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I_0(_rfe)
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I_u2s3u1(_sc)
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I_u2s3u1(_scd)
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@ -427,6 +426,25 @@ I_u1(_syscall);
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I_u1u2s3(_bbit0);
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I_u1u2s3(_bbit1);
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#ifdef CONFIG_CPU_CAVIUM_OCTEON
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#include <asm/octeon/octeon.h>
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void __uasminit uasm_i_pref(u32 **buf, unsigned int a, signed int b,
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unsigned int c)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) && a <= 24 && a != 5)
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/*
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* As per erratum Core-14449, replace prefetches 0-4,
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* 6-24 with 'pref 28'.
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*/
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build_insn(buf, insn_pref, c, 28, b);
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else
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build_insn(buf, insn_pref, c, a, b);
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}
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UASM_EXPORT_SYMBOL(uasm_i_pref);
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#else
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I_u2s3u1(_pref)
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#endif
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/* Handle labels. */
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void __uasminit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid)
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{
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