drm/etnaviv: handle security states
GPUs with support for the security features need some additional setup to get the frontend started. Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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@ -481,9 +481,14 @@ static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
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control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
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gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
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if (gpu->sec_mode == ETNA_SEC_KERNEL) {
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gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
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VIVS_MMUv2_AHB_CONTROL_RESET);
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} else {
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/* set soft reset. */
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control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
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gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
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}
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/* wait for reset. */
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usleep_range(10, 20);
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@ -594,6 +599,12 @@ void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
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gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
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VIVS_FE_COMMAND_CONTROL_ENABLE |
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VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
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if (gpu->sec_mode == ETNA_SEC_KERNEL) {
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gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
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VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
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VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
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}
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}
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static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
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@ -667,6 +678,12 @@ static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
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gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
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}
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if (gpu->sec_mode == ETNA_SEC_KERNEL) {
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u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
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val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
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gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
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}
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/* setup the pulse eater */
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etnaviv_gpu_setup_pulse_eater(gpu);
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@ -729,6 +746,14 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
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gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
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}
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/*
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* On cores with security features supported, we claim control over the
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* security states.
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*/
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if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
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(gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
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gpu->sec_mode = ETNA_SEC_KERNEL;
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ret = etnaviv_hw_reset(gpu);
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if (ret) {
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dev_err(gpu->dev, "GPU reset failed\n");
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@ -1342,17 +1367,30 @@ static void sync_point_worker(struct work_struct *work)
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static void dump_mmu_fault(struct etnaviv_gpu *gpu)
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{
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u32 status = gpu_read(gpu, VIVS_MMUv2_STATUS);
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u32 status_reg, status;
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int i;
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if (gpu->sec_mode == ETNA_SEC_NONE)
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status_reg = VIVS_MMUv2_STATUS;
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else
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status_reg = VIVS_MMUv2_SEC_STATUS;
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status = gpu_read(gpu, status_reg);
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dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
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for (i = 0; i < 4; i++) {
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u32 address_reg;
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if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
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continue;
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if (gpu->sec_mode == ETNA_SEC_NONE)
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address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
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else
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address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
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dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
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gpu_read(gpu, VIVS_MMUv2_EXCEPTION_ADDR(i)));
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gpu_read(gpu, address_reg));
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}
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}
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