USB2NET : SR9700 : One chip USB 1.1 USB2NET SR9700Device Driver Support
Signed-off-by: Liu Junliang <liujunliang_ljl@163.com> Signed-off-by: David S. Miller <davem@davemloft.net>hifive-unleashed-5.1
Liu Junliang
David S. Miller
parent
a77dcb8c8f
commit
c9b37458e9
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@ -268,6 +268,14 @@ config USB_NET_DM9601
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This option adds support for Davicom DM9601 based USB 1.1
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10/100 Ethernet adapters.
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config USB_NET_SR9700
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tristate "CoreChip-sz SR9700 based USB 1.1 10/100 ethernet devices"
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depends on USB_USBNET
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select CRC32
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help
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This option adds support for CoreChip-sz SR9700 based USB 1.1
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10/100 Ethernet adapters.
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config USB_NET_SMSC75XX
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tristate "SMSC LAN75XX based USB 2.0 gigabit ethernet devices"
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depends on USB_USBNET
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@ -14,6 +14,7 @@ obj-$(CONFIG_USB_NET_AX88179_178A) += ax88179_178a.o
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obj-$(CONFIG_USB_NET_CDCETHER) += cdc_ether.o r815x.o
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obj-$(CONFIG_USB_NET_CDC_EEM) += cdc_eem.o
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obj-$(CONFIG_USB_NET_DM9601) += dm9601.o
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obj-$(CONFIG_USB_NET_SR9700) += sr9700.o
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obj-$(CONFIG_USB_NET_SMSC75XX) += smsc75xx.o
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obj-$(CONFIG_USB_NET_SMSC95XX) += smsc95xx.o
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obj-$(CONFIG_USB_NET_GL620A) += gl620a.o
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@ -0,0 +1,560 @@
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/*
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* CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices
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*
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* Author : Liu Junliang <liujunliang_ljl@163.com>
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*
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* Based on dm9601.c
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/module.h>
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#include <linux/sched.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/mii.h>
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#include <linux/usb.h>
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#include <linux/crc32.h>
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#include <linux/usb/usbnet.h>
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#include "sr9700.h"
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static int sr_read(struct usbnet *dev, u8 reg, u16 length, void *data)
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{
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int err;
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err = usbnet_read_cmd(dev, SR_RD_REGS, SR_REQ_RD_REG, 0, reg, data,
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length);
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if ((err != length) && (err >= 0))
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err = -EINVAL;
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return err;
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}
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static int sr_write(struct usbnet *dev, u8 reg, u16 length, void *data)
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{
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int err;
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err = usbnet_write_cmd(dev, SR_WR_REGS, SR_REQ_WR_REG, 0, reg, data,
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length);
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if ((err >= 0) && (err < length))
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err = -EINVAL;
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return err;
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}
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static int sr_read_reg(struct usbnet *dev, u8 reg, u8 *value)
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{
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return sr_read(dev, reg, 1, value);
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}
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static int sr_write_reg(struct usbnet *dev, u8 reg, u8 value)
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{
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return usbnet_write_cmd(dev, SR_WR_REGS, SR_REQ_WR_REG,
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value, reg, NULL, 0);
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}
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static void sr_write_async(struct usbnet *dev, u8 reg, u16 length, void *data)
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{
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usbnet_write_cmd_async(dev, SR_WR_REGS, SR_REQ_WR_REG,
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0, reg, data, length);
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}
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static void sr_write_reg_async(struct usbnet *dev, u8 reg, u8 value)
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{
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usbnet_write_cmd_async(dev, SR_WR_REGS, SR_REQ_WR_REG,
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value, reg, NULL, 0);
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}
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static int wait_phy_eeprom_ready(struct usbnet *dev, int phy)
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{
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int i;
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for (i = 0; i < SR_SHARE_TIMEOUT; i++) {
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u8 tmp = 0;
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int ret;
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udelay(1);
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ret = sr_read_reg(dev, EPCR, &tmp);
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if (ret < 0)
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return ret;
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/* ready */
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if (!(tmp & EPCR_ERRE))
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return 0;
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}
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netdev_err(dev->net, "%s write timed out!\n", phy ? "phy" : "eeprom");
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return -EIO;
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}
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static int sr_share_read_word(struct usbnet *dev, int phy, u8 reg,
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__le16 *value)
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{
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int ret;
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mutex_lock(&dev->phy_mutex);
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sr_write_reg(dev, EPAR, phy ? (reg | EPAR_PHY_ADR) : reg);
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sr_write_reg(dev, EPCR, phy ? (EPCR_EPOS | EPCR_ERPRR) : EPCR_ERPRR);
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ret = wait_phy_eeprom_ready(dev, phy);
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if (ret < 0)
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goto out_unlock;
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sr_write_reg(dev, EPCR, 0x0);
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ret = sr_read(dev, EPDR, 2, value);
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netdev_dbg(dev->net, "read shared %d 0x%02x returned 0x%04x, %d\n",
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phy, reg, *value, ret);
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out_unlock:
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mutex_unlock(&dev->phy_mutex);
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return ret;
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}
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static int sr_share_write_word(struct usbnet *dev, int phy, u8 reg,
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__le16 value)
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{
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int ret;
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mutex_lock(&dev->phy_mutex);
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ret = sr_write(dev, EPDR, 2, &value);
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if (ret < 0)
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goto out_unlock;
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sr_write_reg(dev, EPAR, phy ? (reg | EPAR_PHY_ADR) : reg);
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sr_write_reg(dev, EPCR, phy ? (EPCR_WEP | EPCR_EPOS | EPCR_ERPRW) :
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(EPCR_WEP | EPCR_ERPRW));
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ret = wait_phy_eeprom_ready(dev, phy);
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if (ret < 0)
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goto out_unlock;
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sr_write_reg(dev, EPCR, 0x0);
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out_unlock:
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mutex_unlock(&dev->phy_mutex);
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return ret;
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}
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static int sr_read_eeprom_word(struct usbnet *dev, u8 offset, void *value)
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{
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return sr_share_read_word(dev, 0, offset, value);
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}
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static int sr9700_get_eeprom_len(struct net_device *netdev)
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{
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return SR_EEPROM_LEN;
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}
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static int sr9700_get_eeprom(struct net_device *netdev,
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struct ethtool_eeprom *eeprom, u8 *data)
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{
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struct usbnet *dev = netdev_priv(netdev);
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__le16 *buf = (__le16 *)data;
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int ret = 0;
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int i;
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/* access is 16bit */
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if ((eeprom->offset & 0x01) || (eeprom->len & 0x01))
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return -EINVAL;
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for (i = 0; i < eeprom->len / 2; i++) {
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ret = sr_read_eeprom_word(dev, eeprom->offset / 2 + i, buf + i);
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if (ret < 0)
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break;
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}
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return ret;
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}
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static int sr_mdio_read(struct net_device *netdev, int phy_id, int loc)
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{
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struct usbnet *dev = netdev_priv(netdev);
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__le16 res;
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int rc = 0;
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if (phy_id) {
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netdev_dbg(netdev, "Only internal phy supported\n");
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return 0;
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}
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/* Access NSR_LINKST bit for link status instead of MII_BMSR */
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if (loc == MII_BMSR) {
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u8 value;
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sr_read_reg(dev, NSR, &value);
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if (value & NSR_LINKST)
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rc = 1;
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}
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sr_share_read_word(dev, 1, loc, &res);
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if (rc == 1)
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res = le16_to_cpu(res) | BMSR_LSTATUS;
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else
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res = le16_to_cpu(res) & ~BMSR_LSTATUS;
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netdev_dbg(netdev, "sr_mdio_read() phy_id=0x%02x, loc=0x%02x, returns=0x%04x\n",
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phy_id, loc, res);
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return res;
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}
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static void sr_mdio_write(struct net_device *netdev, int phy_id, int loc,
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int val)
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{
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struct usbnet *dev = netdev_priv(netdev);
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__le16 res = cpu_to_le16(val);
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if (phy_id) {
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netdev_dbg(netdev, "Only internal phy supported\n");
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return;
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}
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netdev_dbg(netdev, "sr_mdio_write() phy_id=0x%02x, loc=0x%02x, val=0x%04x\n",
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phy_id, loc, val);
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sr_share_write_word(dev, 1, loc, res);
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}
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static u32 sr9700_get_link(struct net_device *netdev)
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{
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struct usbnet *dev = netdev_priv(netdev);
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u8 value = 0;
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int rc = 0;
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/* Get the Link Status directly */
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sr_read_reg(dev, NSR, &value);
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if (value & NSR_LINKST)
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rc = 1;
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return rc;
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}
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static int sr9700_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
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{
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struct usbnet *dev = netdev_priv(netdev);
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return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
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}
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static const struct ethtool_ops sr9700_ethtool_ops = {
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.get_drvinfo = usbnet_get_drvinfo,
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.get_link = sr9700_get_link,
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.get_msglevel = usbnet_get_msglevel,
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.set_msglevel = usbnet_set_msglevel,
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.get_eeprom_len = sr9700_get_eeprom_len,
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.get_eeprom = sr9700_get_eeprom,
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.get_settings = usbnet_get_settings,
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.set_settings = usbnet_set_settings,
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.nway_reset = usbnet_nway_reset,
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};
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static void sr9700_set_multicast(struct net_device *netdev)
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{
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struct usbnet *dev = netdev_priv(netdev);
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/* We use the 20 byte dev->data for our 8 byte filter buffer
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* to avoid allocating memory that is tricky to free later
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*/
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u8 *hashes = (u8 *)&dev->data;
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/* rx_ctl setting : enable, disable_long, disable_crc */
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u8 rx_ctl = RCR_RXEN | RCR_DIS_CRC | RCR_DIS_LONG;
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memset(hashes, 0x00, SR_MCAST_SIZE);
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/* broadcast address */
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hashes[SR_MCAST_SIZE - 1] |= SR_MCAST_ADDR_FLAG;
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if (netdev->flags & IFF_PROMISC) {
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rx_ctl |= RCR_PRMSC;
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} else if (netdev->flags & IFF_ALLMULTI ||
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netdev_mc_count(netdev) > SR_MCAST_MAX) {
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rx_ctl |= RCR_RUNT;
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} else if (!netdev_mc_empty(netdev)) {
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struct netdev_hw_addr *ha;
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netdev_for_each_mc_addr(ha, netdev) {
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u32 crc = ether_crc(ETH_ALEN, ha->addr) >> 26;
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hashes[crc >> 3] |= 1 << (crc & 0x7);
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}
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}
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sr_write_async(dev, MAR, SR_MCAST_SIZE, hashes);
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sr_write_reg_async(dev, RCR, rx_ctl);
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}
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static int sr9700_set_mac_address(struct net_device *netdev, void *p)
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{
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struct usbnet *dev = netdev_priv(netdev);
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struct sockaddr *addr = p;
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if (!is_valid_ether_addr(addr->sa_data)) {
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netdev_err(netdev, "not setting invalid mac address %pM\n",
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addr->sa_data);
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return -EINVAL;
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}
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memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
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sr_write_async(dev, PAR, 6, netdev->dev_addr);
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return 0;
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}
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static const struct net_device_ops sr9700_netdev_ops = {
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.ndo_open = usbnet_open,
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.ndo_stop = usbnet_stop,
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.ndo_start_xmit = usbnet_start_xmit,
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.ndo_tx_timeout = usbnet_tx_timeout,
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.ndo_change_mtu = usbnet_change_mtu,
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.ndo_validate_addr = eth_validate_addr,
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.ndo_do_ioctl = sr9700_ioctl,
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.ndo_set_rx_mode = sr9700_set_multicast,
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.ndo_set_mac_address = sr9700_set_mac_address,
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};
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static int sr9700_bind(struct usbnet *dev, struct usb_interface *intf)
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{
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struct net_device *netdev;
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struct mii_if_info *mii;
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int ret;
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ret = usbnet_get_endpoints(dev, intf);
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if (ret)
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goto out;
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netdev = dev->net;
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netdev->netdev_ops = &sr9700_netdev_ops;
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netdev->ethtool_ops = &sr9700_ethtool_ops;
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netdev->hard_header_len += SR_TX_OVERHEAD;
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dev->hard_mtu = netdev->mtu + netdev->hard_header_len;
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/* bulkin buffer is preferably not less than 3K */
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dev->rx_urb_size = 3072;
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mii = &dev->mii;
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mii->dev = netdev;
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mii->mdio_read = sr_mdio_read;
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mii->mdio_write = sr_mdio_write;
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mii->phy_id_mask = 0x1f;
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mii->reg_num_mask = 0x1f;
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sr_write_reg(dev, NCR, NCR_RST);
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udelay(20);
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/* read MAC
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* After Chip Power on, the Chip will reload the MAC from
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* EEPROM automatically to PAR. In case there is no EEPROM externally,
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* a default MAC address is stored in PAR for making chip work properly.
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*/
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if (sr_read(dev, PAR, ETH_ALEN, netdev->dev_addr) < 0) {
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netdev_err(netdev, "Error reading MAC address\n");
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ret = -ENODEV;
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goto out;
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}
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/* power up and reset phy */
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sr_write_reg(dev, PRR, PRR_PHY_RST);
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/* at least 10ms, here 20ms for safe */
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mdelay(20);
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sr_write_reg(dev, PRR, 0);
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/* at least 1ms, here 2ms for reading right register */
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udelay(2 * 1000);
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/* receive broadcast packets */
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sr9700_set_multicast(netdev);
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sr_mdio_write(netdev, mii->phy_id, MII_BMCR, BMCR_RESET);
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sr_mdio_write(netdev, mii->phy_id, MII_ADVERTISE, ADVERTISE_ALL |
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ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
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mii_nway_restart(mii);
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out:
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return ret;
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}
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static int sr9700_rx_fixup(struct usbnet *dev, struct sk_buff *skb)
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{
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struct sk_buff *sr_skb;
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int len;
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/* skb content (packets) format :
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* p0 p1 p2 ...... pm
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* / \
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* / \
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* / \
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* / \
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* p0b0 p0b1 p0b2 p0b3 ...... p0b(n-4) p0b(n-3)...p0bn
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*
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* p0 : packet 0
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* p0b0 : packet 0 byte 0
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*
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* b0: rx status
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* b1: packet length (incl crc) low
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* b2: packet length (incl crc) high
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* b3..n-4: packet data
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* bn-3..bn: ethernet packet crc
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*/
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if (unlikely(skb->len < SR_RX_OVERHEAD)) {
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netdev_err(dev->net, "unexpected tiny rx frame\n");
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return 0;
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}
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/* one skb may contains multiple packets */
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while (skb->len > SR_RX_OVERHEAD) {
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if (skb->data[0] != 0x40)
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return 0;
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/* ignore the CRC length */
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len = (skb->data[1] | (skb->data[2] << 8)) - 4;
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if (len > ETH_FRAME_LEN)
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return 0;
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/* the last packet of current skb */
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if (skb->len == (len + SR_RX_OVERHEAD)) {
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skb_pull(skb, 3);
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skb->len = len;
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skb_set_tail_pointer(skb, len);
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skb->truesize = len + sizeof(struct sk_buff);
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return 2;
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}
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/* skb_clone is used for address align */
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sr_skb = skb_clone(skb, GFP_ATOMIC);
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if (!sr_skb)
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return 0;
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sr_skb->len = len;
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sr_skb->data = skb->data + 3;
|
||||
skb_set_tail_pointer(sr_skb, len);
|
||||
sr_skb->truesize = len + sizeof(struct sk_buff);
|
||||
usbnet_skb_return(dev, sr_skb);
|
||||
|
||||
skb_pull(skb, len + SR_RX_OVERHEAD);
|
||||
};
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sk_buff *sr9700_tx_fixup(struct usbnet *dev, struct sk_buff *skb,
|
||||
gfp_t flags)
|
||||
{
|
||||
int len;
|
||||
|
||||
/* SR9700 can only send out one ethernet packet at once.
|
||||
*
|
||||
* b0 b1 b2 b3 ...... b(n-4) b(n-3)...bn
|
||||
*
|
||||
* b0: rx status
|
||||
* b1: packet length (incl crc) low
|
||||
* b2: packet length (incl crc) high
|
||||
* b3..n-4: packet data
|
||||
* bn-3..bn: ethernet packet crc
|
||||
*/
|
||||
|
||||
len = skb->len;
|
||||
|
||||
if (skb_headroom(skb) < SR_TX_OVERHEAD) {
|
||||
struct sk_buff *skb2;
|
||||
|
||||
skb2 = skb_copy_expand(skb, SR_TX_OVERHEAD, 0, flags);
|
||||
dev_kfree_skb_any(skb);
|
||||
skb = skb2;
|
||||
if (!skb)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
__skb_push(skb, SR_TX_OVERHEAD);
|
||||
|
||||
/* usbnet adds padding if length is a multiple of packet size
|
||||
* if so, adjust length value in header
|
||||
*/
|
||||
if ((skb->len % dev->maxpacket) == 0)
|
||||
len++;
|
||||
|
||||
skb->data[0] = len;
|
||||
skb->data[1] = len >> 8;
|
||||
|
||||
return skb;
|
||||
}
|
||||
|
||||
static void sr9700_status(struct usbnet *dev, struct urb *urb)
|
||||
{
|
||||
int link;
|
||||
u8 *buf;
|
||||
|
||||
/* format:
|
||||
b0: net status
|
||||
b1: tx status 1
|
||||
b2: tx status 2
|
||||
b3: rx status
|
||||
b4: rx overflow
|
||||
b5: rx count
|
||||
b6: tx count
|
||||
b7: gpr
|
||||
*/
|
||||
|
||||
if (urb->actual_length < 8)
|
||||
return;
|
||||
|
||||
buf = urb->transfer_buffer;
|
||||
|
||||
link = !!(buf[0] & 0x40);
|
||||
if (netif_carrier_ok(dev->net) != link) {
|
||||
usbnet_link_change(dev, link, 1);
|
||||
netdev_dbg(dev->net, "Link Status is: %d\n", link);
|
||||
}
|
||||
}
|
||||
|
||||
static int sr9700_link_reset(struct usbnet *dev)
|
||||
{
|
||||
struct ethtool_cmd ecmd;
|
||||
|
||||
mii_check_media(&dev->mii, 1, 1);
|
||||
mii_ethtool_gset(&dev->mii, &ecmd);
|
||||
|
||||
netdev_dbg(dev->net, "link_reset() speed: %d duplex: %d\n",
|
||||
ecmd.speed, ecmd.duplex);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct driver_info sr9700_driver_info = {
|
||||
.description = "CoreChip SR9700 USB Ethernet",
|
||||
.flags = FLAG_ETHER,
|
||||
.bind = sr9700_bind,
|
||||
.rx_fixup = sr9700_rx_fixup,
|
||||
.tx_fixup = sr9700_tx_fixup,
|
||||
.status = sr9700_status,
|
||||
.link_reset = sr9700_link_reset,
|
||||
.reset = sr9700_link_reset,
|
||||
};
|
||||
|
||||
static const struct usb_device_id products[] = {
|
||||
{
|
||||
USB_DEVICE(0x0fe6, 0x9700), /* SR9700 device */
|
||||
.driver_info = (unsigned long)&sr9700_driver_info,
|
||||
},
|
||||
{}, /* END */
|
||||
};
|
||||
|
||||
MODULE_DEVICE_TABLE(usb, products);
|
||||
|
||||
static struct usb_driver sr9700_usb_driver = {
|
||||
.name = "sr9700",
|
||||
.id_table = products,
|
||||
.probe = usbnet_probe,
|
||||
.disconnect = usbnet_disconnect,
|
||||
.suspend = usbnet_suspend,
|
||||
.resume = usbnet_resume,
|
||||
.disable_hub_initiated_lpm = 1,
|
||||
};
|
||||
|
||||
module_usb_driver(sr9700_usb_driver);
|
||||
|
||||
MODULE_AUTHOR("liujl <liujunliang_ljl@163.com>");
|
||||
MODULE_DESCRIPTION("SR9700 one chip USB 1.1 USB to Ethernet device from http://www.corechip-sz.com/");
|
||||
MODULE_LICENSE("GPL");
|
||||
|
|
@ -0,0 +1,173 @@
|
|||
/*
|
||||
* CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices
|
||||
*
|
||||
* Author : Liu Junliang <liujunliang_ljl@163.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License
|
||||
* version 2 as published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _SR9700_H
|
||||
#define _SR9700_H
|
||||
|
||||
/* sr9700 spec. register table on Linux platform */
|
||||
|
||||
/* Network Control Reg */
|
||||
#define NCR 0x00
|
||||
#define NCR_RST (1 << 0)
|
||||
#define NCR_LBK (3 << 1)
|
||||
#define NCR_FDX (1 << 3)
|
||||
#define NCR_WAKEEN (1 << 6)
|
||||
/* Network Status Reg */
|
||||
#define NSR 0x01
|
||||
#define NSR_RXRDY (1 << 0)
|
||||
#define NSR_RXOV (1 << 1)
|
||||
#define NSR_TX1END (1 << 2)
|
||||
#define NSR_TX2END (1 << 3)
|
||||
#define NSR_TXFULL (1 << 4)
|
||||
#define NSR_WAKEST (1 << 5)
|
||||
#define NSR_LINKST (1 << 6)
|
||||
#define NSR_SPEED (1 << 7)
|
||||
/* Tx Control Reg */
|
||||
#define TCR 0x02
|
||||
#define TCR_CRC_DIS (1 << 1)
|
||||
#define TCR_PAD_DIS (1 << 2)
|
||||
#define TCR_LC_CARE (1 << 3)
|
||||
#define TCR_CRS_CARE (1 << 4)
|
||||
#define TCR_EXCECM (1 << 5)
|
||||
#define TCR_LF_EN (1 << 6)
|
||||
/* Tx Status Reg for Packet Index 1 */
|
||||
#define TSR1 0x03
|
||||
#define TSR1_EC (1 << 2)
|
||||
#define TSR1_COL (1 << 3)
|
||||
#define TSR1_LC (1 << 4)
|
||||
#define TSR1_NC (1 << 5)
|
||||
#define TSR1_LOC (1 << 6)
|
||||
#define TSR1_TLF (1 << 7)
|
||||
/* Tx Status Reg for Packet Index 2 */
|
||||
#define TSR2 0x04
|
||||
#define TSR2_EC (1 << 2)
|
||||
#define TSR2_COL (1 << 3)
|
||||
#define TSR2_LC (1 << 4)
|
||||
#define TSR2_NC (1 << 5)
|
||||
#define TSR2_LOC (1 << 6)
|
||||
#define TSR2_TLF (1 << 7)
|
||||
/* Rx Control Reg*/
|
||||
#define RCR 0x05
|
||||
#define RCR_RXEN (1 << 0)
|
||||
#define RCR_PRMSC (1 << 1)
|
||||
#define RCR_RUNT (1 << 2)
|
||||
#define RCR_ALL (1 << 3)
|
||||
#define RCR_DIS_CRC (1 << 4)
|
||||
#define RCR_DIS_LONG (1 << 5)
|
||||
/* Rx Status Reg */
|
||||
#define RSR 0x06
|
||||
#define RSR_AE (1 << 2)
|
||||
#define RSR_MF (1 << 6)
|
||||
#define RSR_RF (1 << 7)
|
||||
/* Rx Overflow Counter Reg */
|
||||
#define ROCR 0x07
|
||||
#define ROCR_ROC (0x7F << 0)
|
||||
#define ROCR_RXFU (1 << 7)
|
||||
/* Back Pressure Threshold Reg */
|
||||
#define BPTR 0x08
|
||||
#define BPTR_JPT (0x0F << 0)
|
||||
#define BPTR_BPHW (0x0F << 4)
|
||||
/* Flow Control Threshold Reg */
|
||||
#define FCTR 0x09
|
||||
#define FCTR_LWOT (0x0F << 0)
|
||||
#define FCTR_HWOT (0x0F << 4)
|
||||
/* rx/tx Flow Control Reg */
|
||||
#define FCR 0x0A
|
||||
#define FCR_FLCE (1 << 0)
|
||||
#define FCR_BKPA (1 << 4)
|
||||
#define FCR_TXPEN (1 << 5)
|
||||
#define FCR_TXPF (1 << 6)
|
||||
#define FCR_TXP0 (1 << 7)
|
||||
/* Eeprom & Phy Control Reg */
|
||||
#define EPCR 0x0B
|
||||
#define EPCR_ERRE (1 << 0)
|
||||
#define EPCR_ERPRW (1 << 1)
|
||||
#define EPCR_ERPRR (1 << 2)
|
||||
#define EPCR_EPOS (1 << 3)
|
||||
#define EPCR_WEP (1 << 4)
|
||||
/* Eeprom & Phy Address Reg */
|
||||
#define EPAR 0x0C
|
||||
#define EPAR_EROA (0x3F << 0)
|
||||
#define EPAR_PHY_ADR_MASK (0x03 << 6)
|
||||
#define EPAR_PHY_ADR (0x01 << 6)
|
||||
/* Eeprom & Phy Data Reg */
|
||||
#define EPDR 0x0D /* 0x0D ~ 0x0E for Data Reg Low & High */
|
||||
/* Wakeup Control Reg */
|
||||
#define WCR 0x0F
|
||||
#define WCR_MAGICST (1 << 0)
|
||||
#define WCR_LINKST (1 << 2)
|
||||
#define WCR_MAGICEN (1 << 3)
|
||||
#define WCR_LINKEN (1 << 5)
|
||||
/* Physical Address Reg */
|
||||
#define PAR 0x10 /* 0x10 ~ 0x15 6 bytes for PAR */
|
||||
/* Multicast Address Reg */
|
||||
#define MAR 0x16 /* 0x16 ~ 0x1D 8 bytes for MAR */
|
||||
/* 0x1e unused */
|
||||
/* Phy Reset Reg */
|
||||
#define PRR 0x1F
|
||||
#define PRR_PHY_RST (1 << 0)
|
||||
/* Tx sdram Write Pointer Address Low */
|
||||
#define TWPAL 0x20
|
||||
/* Tx sdram Write Pointer Address High */
|
||||
#define TWPAH 0x21
|
||||
/* Tx sdram Read Pointer Address Low */
|
||||
#define TRPAL 0x22
|
||||
/* Tx sdram Read Pointer Address High */
|
||||
#define TRPAH 0x23
|
||||
/* Rx sdram Write Pointer Address Low */
|
||||
#define RWPAL 0x24
|
||||
/* Rx sdram Write Pointer Address High */
|
||||
#define RWPAH 0x25
|
||||
/* Rx sdram Read Pointer Address Low */
|
||||
#define RRPAL 0x26
|
||||
/* Rx sdram Read Pointer Address High */
|
||||
#define RRPAH 0x27
|
||||
/* Vendor ID register */
|
||||
#define VID 0x28 /* 0x28 ~ 0x29 2 bytes for VID */
|
||||
/* Product ID register */
|
||||
#define PID 0x2A /* 0x2A ~ 0x2B 2 bytes for PID */
|
||||
/* CHIP Revision register */
|
||||
#define CHIPR 0x2C
|
||||
/* 0x2D --> 0xEF unused */
|
||||
/* USB Device Address */
|
||||
#define USBDA 0xF0
|
||||
#define USBDA_USBFA (0x7F << 0)
|
||||
/* RX packet Counter Reg */
|
||||
#define RXC 0xF1
|
||||
/* Tx packet Counter & USB Status Reg */
|
||||
#define TXC_USBS 0xF2
|
||||
#define TXC_USBS_TXC0 (1 << 0)
|
||||
#define TXC_USBS_TXC1 (1 << 1)
|
||||
#define TXC_USBS_TXC2 (1 << 2)
|
||||
#define TXC_USBS_EP1RDY (1 << 5)
|
||||
#define TXC_USBS_SUSFLAG (1 << 6)
|
||||
#define TXC_USBS_RXFAULT (1 << 7)
|
||||
/* USB Control register */
|
||||
#define USBC 0xF4
|
||||
#define USBC_EP3NAK (1 << 4)
|
||||
#define USBC_EP3ACK (1 << 5)
|
||||
|
||||
/* Register access commands and flags */
|
||||
#define SR_RD_REGS 0x00
|
||||
#define SR_WR_REGS 0x01
|
||||
#define SR_WR_REG 0x03
|
||||
#define SR_REQ_RD_REG (USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
|
||||
#define SR_REQ_WR_REG (USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE)
|
||||
|
||||
/* parameters */
|
||||
#define SR_SHARE_TIMEOUT 1000
|
||||
#define SR_EEPROM_LEN 256
|
||||
#define SR_MCAST_SIZE 8
|
||||
#define SR_MCAST_ADDR_FLAG 0x80
|
||||
#define SR_MCAST_MAX 64
|
||||
#define SR_TX_OVERHEAD 2 /* 2bytes header */
|
||||
#define SR_RX_OVERHEAD 7 /* 3bytes header + 4crc tail */
|
||||
|
||||
#endif /* _SR9700_H */
|
||||
Loading…
Reference in New Issue