b43: N-PHY: implement enabling TX power control
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
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@ -248,15 +248,25 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
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{
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struct b43_phy_n *nphy = dev->phy.n;
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u8 i;
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u16 tmp;
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u16 bmask, val, tmp;
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enum ieee80211_band band = b43_current_band(dev->wl);
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if (nphy->hang_avoid)
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b43_nphy_stay_in_carrier_search(dev, 1);
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nphy->txpwrctrl = enable;
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if (!enable) {
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if (dev->phy.rev >= 3)
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; /* TODO */
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if (dev->phy.rev >= 3 &&
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(b43_phy_read(dev, B43_NPHY_TXPCTL_CMD) &
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(B43_NPHY_TXPCTL_CMD_COEFF |
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B43_NPHY_TXPCTL_CMD_HWPCTLEN |
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B43_NPHY_TXPCTL_CMD_PCTLEN))) {
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/* We disable enabled TX pwr ctl, save it's state */
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nphy->tx_pwr_idx[0] = b43_phy_read(dev,
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B43_NPHY_C1_TXPCTL_STAT) & 0x7f;
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nphy->tx_pwr_idx[1] = b43_phy_read(dev,
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B43_NPHY_C2_TXPCTL_STAT) & 0x7f;
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}
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b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x6840);
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for (i = 0; i < 84; i++)
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@ -285,10 +295,68 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
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b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
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~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
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if (dev->phy.rev < 2 && 0)
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; /* TODO */
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if (dev->phy.rev < 2 && dev->phy.is_40mhz)
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b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
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} else {
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b43err(dev->wl, "enabling tx pwr ctrl not implemented yet\n");
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b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
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nphy->adj_pwr_tbl);
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b43_ntab_write_bulk(dev, B43_NTAB16(27, 64), 84,
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nphy->adj_pwr_tbl);
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bmask = B43_NPHY_TXPCTL_CMD_COEFF |
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B43_NPHY_TXPCTL_CMD_HWPCTLEN;
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/* wl does useless check for "enable" param here */
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val = B43_NPHY_TXPCTL_CMD_COEFF | B43_NPHY_TXPCTL_CMD_HWPCTLEN;
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if (dev->phy.rev >= 3) {
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bmask |= B43_NPHY_TXPCTL_CMD_PCTLEN;
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if (val)
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val |= B43_NPHY_TXPCTL_CMD_PCTLEN;
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}
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b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD, ~(bmask), val);
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if (band == IEEE80211_BAND_5GHZ) {
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b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
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~B43_NPHY_TXPCTL_CMD_INIT, 0x64);
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if (dev->phy.rev > 1)
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b43_phy_maskset(dev, B43_NPHY_TXPCTL_INIT,
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~B43_NPHY_TXPCTL_INIT_PIDXI1,
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0x64);
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}
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if (dev->phy.rev >= 3) {
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if (nphy->tx_pwr_idx[0] != 128 &&
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nphy->tx_pwr_idx[1] != 128) {
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/* Recover TX pwr ctl state */
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b43_phy_maskset(dev, B43_NPHY_TXPCTL_CMD,
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~B43_NPHY_TXPCTL_CMD_INIT,
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nphy->tx_pwr_idx[0]);
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if (dev->phy.rev > 1)
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b43_phy_maskset(dev,
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B43_NPHY_TXPCTL_INIT,
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~0xff, nphy->tx_pwr_idx[1]);
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}
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}
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if (dev->phy.rev >= 3) {
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b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, ~0x100);
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b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x100);
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} else {
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b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, ~0x4000);
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}
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if (dev->phy.rev == 2)
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b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x3b);
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else if (dev->phy.rev < 2)
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b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
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if (dev->phy.rev < 2 && dev->phy.is_40mhz)
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b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
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if ((nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
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(nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ)) {
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b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x4);
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b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x4);
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}
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}
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if (nphy->hang_avoid)
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@ -3918,6 +3986,10 @@ static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
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nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
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nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
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nphy->perical = 2; /* avoid additional rssi cal on init (like wl) */
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/* 128 can mean disabled-by-default state of TX pwr ctl. Max value is
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* 0x7f == 127 and we check for 128 when restoring TX pwr ctl. */
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nphy->tx_pwr_idx[0] = 128;
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nphy->tx_pwr_idx[1] = 128;
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}
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static void b43_nphy_op_free(struct b43_wldev *dev)
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@ -783,6 +783,8 @@ struct b43_phy_n {
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u16 mphase_txcal_bestcoeffs[11];
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bool txpwrctrl;
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u8 tx_pwr_idx[2];
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u16 adj_pwr_tbl[84];
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u16 txcal_bbmult;
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u16 txiqlocal_bestc[11];
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bool txiqlocal_coeffsvalid;
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