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[PATCH] Do not enforce unique IO_APIC_ID check for xAPIC systems (i386) 

This patch is per Andi's request to remove NO_IOAPIC_CHECK from genapic and
use heuristics to prevent unique I/O APIC ID check for systems that don't
need it.  The patch disables unique I/O APIC ID check for Xeon-based and
other platforms that don't use serial APIC bus for interrupt delivery.
Andi stated that AMD systems don't need unique IO_APIC_IDs either.

Signed-off-by: Natalie Protasevich <Natalie.Protasevich@unisys.com>
Cc: Andi Kleen <ak@muc.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
hifive-unleashed-5.1
Natalie Protasevich 2005-06-23 00:08:22 -07:00 committed by Linus Torvalds
parent 7c1def1652
commit ca05fea6db
10 changed files with 10 additions and 19 deletions
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10
arch/i386/kernel/io_apic.c
View File

@ -1658,6 +1658,12 @@ static void __init setup_ioapic_ids_from_mpc(void)
unsigned char old_id;
unsigned long flags;
/*
* Don't check I/O APIC IDs for xAPIC systems. They have
* no meaning without the serial APIC bus.
*/
if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && boot_cpu_data.x86 < 15))
return;
/*
* This is broken; anything with a real cpu count has to
* circumvent this idiocy regardless.
@ -1684,10 +1690,6 @@ static void __init setup_ioapic_ids_from_mpc(void)
mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
}
/* Don't check I/O APIC IDs for some xAPIC systems. They have
* no meaning without the serial APIC bus. */
if (NO_IOAPIC_CHECK)
continue;
/*
* Sanity check, is the ID really free? Every APIC in a
* system must have a unique ID or we get lots of nice

5
arch/i386/kernel/mpparse.c
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@ -914,7 +914,10 @@ void __init mp_register_ioapic (
mp_ioapics[idx].mpc_apicaddr = address;
set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 < 15))
mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
else
mp_ioapics[idx].mpc_apicid = id;
mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
/*

1
include/asm-i386/genapic.h
View File

@ -78,7 +78,6 @@ struct genapic {
.int_delivery_mode = INT_DELIVERY_MODE, \
.int_dest_mode = INT_DEST_MODE, \
.no_balance_irq = NO_BALANCE_IRQ, \
.no_ioapic_check = NO_IOAPIC_CHECK, \
.ESR_DISABLE = esr_disable, \
.apic_destination_logical = APIC_DEST_LOGICAL, \
APICFUNC(apic_id_registered), \

2
include/asm-i386/mach-bigsmp/mach_apic.h
View File

@ -14,8 +14,6 @@
#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
#define NO_IOAPIC_CHECK (0)
static inline int apic_id_registered(void)
{
return (1);

2
include/asm-i386/mach-default/mach_apic.h
View File

@ -19,8 +19,6 @@ static inline cpumask_t target_cpus(void)
#define NO_BALANCE_IRQ (0)
#define esr_disable (0)
#define NO_IOAPIC_CHECK (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */

2
include/asm-i386/mach-es7000/mach_apic.h
View File

@ -38,8 +38,6 @@ static inline cpumask_t target_cpus(void)
#define WAKE_SECONDARY_VIA_INIT
#endif
#define NO_IOAPIC_CHECK (1)
static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
{
return 0;

1
include/asm-i386/mach-generic/mach_apic.h
View File

@ -5,7 +5,6 @@
#define esr_disable (genapic->ESR_DISABLE)
#define NO_BALANCE_IRQ (genapic->no_balance_irq)
#define NO_IOAPIC_CHECK (genapic->no_ioapic_check)
#define INT_DELIVERY_MODE (genapic->int_delivery_mode)
#define INT_DEST_MODE (genapic->int_dest_mode)
#undef APIC_DEST_LOGICAL

2
include/asm-i386/mach-numaq/mach_apic.h
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@ -17,8 +17,6 @@ static inline cpumask_t target_cpus(void)
#define NO_BALANCE_IRQ (1)
#define esr_disable (1)
#define NO_IOAPIC_CHECK (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 0 /* physical delivery on LOCAL quad */

2
include/asm-i386/mach-summit/mach_apic.h
View File

@ -7,8 +7,6 @@
#define esr_disable (1)
#define NO_BALANCE_IRQ (0)
#define NO_IOAPIC_CHECK (1) /* Don't check I/O APIC ID for xAPIC */
/* In clustered mode, the high nibble of APIC ID is a cluster number.
* The low nibble is a 4-bit bitmap. */
#define XAPIC_DEST_CPUS_SHIFT 4

2
include/asm-i386/mach-visws/mach_apic.h
View File

@ -9,8 +9,6 @@
#define no_balance_irq (0)
#define esr_disable (0)
#define NO_IOAPIC_CHECK (0)
#define INT_DELIVERY_MODE dest_LowestPrio
#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */