Ability to build the clock driver as module and removal
of an unused parent-names struct. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAl9ryPgQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgf8pB/sHargsQfzU+4jkcHx8/RSbitJ79jkwcOay np8xCD8lS0z794xvpxuw/zEECuwCHXmZvfw3teoIgVrYWcG2IHK8PyJe0EoAQYRj ox+B4lhleG5qs5noIFUSqAIdMbe6+8dEMsz+0+nWTFVSy/japY8CqiuUUArGfu+a D2jwgy+Ck2T4+7IvBdC7dNbq7FUHnk/FnPKxXo/6jTZU8wSIb2YIBrg1VtIjMnx9 etH6fKt/WLpELQD6x8b4bebrO1bvxjhcnPVdtaJ6+pTYRxb3k8OGnSO4k2ie6zjS D1PPVlDLd3rpjJMJVH6ztaEjJ7e1te+wD0TRuKn5H/XbrKbPDdR6 =kUo/ -----END PGP SIGNATURE----- Merge tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Ability to build the clock driver as module and removal of an unused parent-names struct. * tag 'v5.10-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3399: Support module build clk: rockchip: fix the clk config to support module build clk: rockchip: Export some clock common APIs for module drivers clk: rockchip: Export rockchip_register_softrst() clk: rockchip: Export rockchip_clk_register_ddrclk() clk: rockchip: Use clk_hw_register_composite instead of clk_register_composite calls clk: rockchip: rk3308: drop unused mux_timer_src_pzero-sugar-mainline-defconfig
commit
ca52a47af6
|
@ -373,6 +373,7 @@ source "drivers/clk/meson/Kconfig"
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source "drivers/clk/mvebu/Kconfig"
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source "drivers/clk/qcom/Kconfig"
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source "drivers/clk/renesas/Kconfig"
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source "drivers/clk/rockchip/Kconfig"
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source "drivers/clk/samsung/Kconfig"
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source "drivers/clk/sifive/Kconfig"
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source "drivers/clk/sprd/Kconfig"
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@ -0,0 +1,78 @@
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# SPDX-License-Identifier: GPL-2.0
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# common clock support for ROCKCHIP SoC family.
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config COMMON_CLK_ROCKCHIP
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bool "Rockchip clock controller common support"
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depends on ARCH_ROCKCHIP
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default ARCH_ROCKCHIP
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help
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Say y here to enable common clock controller for Rockchip platforms.
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if COMMON_CLK_ROCKCHIP
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config CLK_PX30
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bool "Rockchip PX30 clock controller support"
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default y
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help
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Build the driver for PX30 Clock Driver.
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config CLK_RV110X
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bool "Rockchip RV110x clock controller support"
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default y
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help
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Build the driver for RV110x Clock Driver.
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config CLK_RK3036
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bool "Rockchip RK3036 clock controller support"
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default y
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help
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Build the driver for RK3036 Clock Driver.
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config CLK_RK312X
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bool "Rockchip RK312x clock controller support"
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default y
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help
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Build the driver for RK312x Clock Driver.
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config CLK_RK3188
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bool "Rockchip RK3188 clock controller support"
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default y
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help
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Build the driver for RK3188 Clock Driver.
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config CLK_RK322X
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bool "Rockchip RK322x clock controller support"
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default y
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help
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Build the driver for RK322x Clock Driver.
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config CLK_RK3288
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bool "Rockchip RK3288 clock controller support"
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depends on ARM
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default y
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help
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Build the driver for RK3288 Clock Driver.
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config CLK_RK3308
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bool "Rockchip RK3308 clock controller support"
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default y
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help
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Build the driver for RK3308 Clock Driver.
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config CLK_RK3328
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bool "Rockchip RK3328 clock controller support"
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default y
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help
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Build the driver for RK3328 Clock Driver.
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config CLK_RK3368
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bool "Rockchip RK3368 clock controller support"
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default y
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help
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Build the driver for RK3368 Clock Driver.
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config CLK_RK3399
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tristate "Rockchip RK3399 clock controller support"
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default y
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help
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Build the driver for RK3399 Clock Driver.
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endif
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@ -3,24 +3,26 @@
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# Rockchip Clock specific Makefile
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#
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obj-y += clk.o
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obj-y += clk-pll.o
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obj-y += clk-cpu.o
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obj-y += clk-half-divider.o
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obj-y += clk-inverter.o
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obj-y += clk-mmc-phase.o
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obj-y += clk-muxgrf.o
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obj-y += clk-ddr.o
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obj-$(CONFIG_RESET_CONTROLLER) += softrst.o
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obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += clk-rockchip.o
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obj-y += clk-px30.o
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obj-y += clk-rv1108.o
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obj-y += clk-rk3036.o
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obj-y += clk-rk3128.o
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obj-y += clk-rk3188.o
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obj-y += clk-rk3228.o
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obj-y += clk-rk3288.o
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obj-y += clk-rk3308.o
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obj-y += clk-rk3328.o
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obj-y += clk-rk3368.o
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obj-y += clk-rk3399.o
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clk-rockchip-y += clk.o
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clk-rockchip-y += clk-pll.o
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clk-rockchip-y += clk-cpu.o
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clk-rockchip-y += clk-half-divider.o
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clk-rockchip-y += clk-inverter.o
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clk-rockchip-y += clk-mmc-phase.o
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clk-rockchip-y += clk-muxgrf.o
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clk-rockchip-y += clk-ddr.o
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clk-rockchip-$(CONFIG_RESET_CONTROLLER) += softrst.o
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obj-$(CONFIG_CLK_PX30) += clk-px30.o
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obj-$(CONFIG_CLK_RV110X) += clk-rv1108.o
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obj-$(CONFIG_CLK_RK3036) += clk-rk3036.o
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obj-$(CONFIG_CLK_RK312X) += clk-rk3128.o
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obj-$(CONFIG_CLK_RK3188) += clk-rk3188.o
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obj-$(CONFIG_CLK_RK322X) += clk-rk3228.o
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obj-$(CONFIG_CLK_RK3288) += clk-rk3288.o
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obj-$(CONFIG_CLK_RK3308) += clk-rk3308.o
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obj-$(CONFIG_CLK_RK3328) += clk-rk3328.o
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obj-$(CONFIG_CLK_RK3368) += clk-rk3368.o
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obj-$(CONFIG_CLK_RK3399) += clk-rk3399.o
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@ -136,3 +136,4 @@ struct clk *rockchip_clk_register_ddrclk(const char *name, int flags,
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return clk;
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}
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EXPORT_SYMBOL_GPL(rockchip_clk_register_ddrclk);
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@ -166,7 +166,7 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
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unsigned long flags,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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@ -212,16 +212,18 @@ struct clk *rockchip_clk_register_halfdiv(const char *name,
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div_ops = &clk_half_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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if (IS_ERR(hw))
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goto err_div;
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return clk;
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return hw->clk;
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err_div:
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kfree(gate);
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err_gate:
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kfree(mux);
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return ERR_PTR(-ENOMEM);
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return ERR_CAST(hw);
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}
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@ -133,7 +133,6 @@ PNAME(mux_uart1_p) = { "clk_uart1_src", "dummy", "clk_uart1_frac" };
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PNAME(mux_uart2_p) = { "clk_uart2_src", "dummy", "clk_uart2_frac" };
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PNAME(mux_uart3_p) = { "clk_uart3_src", "dummy", "clk_uart3_frac" };
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PNAME(mux_uart4_p) = { "clk_uart4_src", "dummy", "clk_uart4_frac" };
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PNAME(mux_timer_src_p) = { "xin24m", "clk_rtc32k" };
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PNAME(mux_dclk_vop_p) = { "dclk_vop_src", "dclk_vop_frac", "xin24m" };
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PNAME(mux_nandc_p) = { "clk_nandc_div", "clk_nandc_div50" };
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PNAME(mux_sdmmc_p) = { "clk_sdmmc_div", "clk_sdmmc_div50" };
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@ -5,9 +5,11 @@
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/rk3399-cru.h>
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@ -1600,3 +1602,57 @@ static void __init rk3399_pmu_clk_init(struct device_node *np)
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rockchip_clk_of_add_provider(np, ctx);
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}
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CLK_OF_DECLARE(rk3399_cru_pmu, "rockchip,rk3399-pmucru", rk3399_pmu_clk_init);
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struct clk_rk3399_inits {
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void (*inits)(struct device_node *np);
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};
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static const struct clk_rk3399_inits clk_rk3399_pmucru_init = {
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.inits = rk3399_pmu_clk_init,
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};
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static const struct clk_rk3399_inits clk_rk3399_cru_init = {
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.inits = rk3399_clk_init,
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};
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static const struct of_device_id clk_rk3399_match_table[] = {
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{
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.compatible = "rockchip,rk3399-cru",
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.data = &clk_rk3399_cru_init,
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}, {
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.compatible = "rockchip,rk3399-pmucru",
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.data = &clk_rk3399_pmucru_init,
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},
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{ }
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};
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MODULE_DEVICE_TABLE(of, clk_rk3399_match_table);
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static int __init clk_rk3399_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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const struct of_device_id *match;
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const struct clk_rk3399_inits *init_data;
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match = of_match_device(clk_rk3399_match_table, &pdev->dev);
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if (!match || !match->data)
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return -EINVAL;
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init_data = match->data;
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if (init_data->inits)
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init_data->inits(np);
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return 0;
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}
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static struct platform_driver clk_rk3399_driver = {
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.driver = {
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.name = "clk-rk3399",
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.of_match_table = clk_rk3399_match_table,
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.suppress_bind_attrs = true,
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},
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};
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builtin_platform_driver_probe(clk_rk3399_driver, clk_rk3399_probe);
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MODULE_DESCRIPTION("Rockchip RK3399 Clock Driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:clk-rk3399");
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@ -43,7 +43,7 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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u8 gate_shift, u8 gate_flags, unsigned long flags,
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spinlock_t *lock)
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{
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_mux *mux = NULL;
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struct clk_gate *gate = NULL;
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struct clk_divider *div = NULL;
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@ -100,20 +100,18 @@ static struct clk *rockchip_clk_register_branch(const char *name,
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: &clk_divider_ops;
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}
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clk = clk_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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goto err_composite;
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hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
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mux ? &mux->hw : NULL, mux_ops,
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div ? &div->hw : NULL, div_ops,
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gate ? &gate->hw : NULL, gate_ops,
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flags);
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||||
if (IS_ERR(hw)) {
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kfree(div);
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kfree(gate);
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||||
return ERR_CAST(hw);
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}
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||||
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||||
return clk;
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err_composite:
|
||||
kfree(div);
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return hw->clk;
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||||
err_div:
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||||
kfree(gate);
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||||
err_gate:
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||||
|
@ -214,8 +212,8 @@ static struct clk *rockchip_clk_register_frac_branch(
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|||
unsigned long flags, struct rockchip_clk_branch *child,
|
||||
spinlock_t *lock)
|
||||
{
|
||||
struct clk_hw *hw;
|
||||
struct rockchip_clk_frac *frac;
|
||||
struct clk *clk;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_fractional_divider *div = NULL;
|
||||
const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
|
||||
|
@ -255,14 +253,14 @@ static struct clk *rockchip_clk_register_frac_branch(
|
|||
div->approximation = rockchip_fractional_approximation;
|
||||
div_ops = &clk_fractional_divider_ops;
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&div->hw, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags | CLK_SET_RATE_UNGATE);
|
||||
if (IS_ERR(clk)) {
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&div->hw, div_ops,
|
||||
gate ? &gate->hw : NULL, gate_ops,
|
||||
flags | CLK_SET_RATE_UNGATE);
|
||||
if (IS_ERR(hw)) {
|
||||
kfree(frac);
|
||||
return clk;
|
||||
return ERR_CAST(hw);
|
||||
}
|
||||
|
||||
if (child) {
|
||||
|
@ -292,7 +290,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
|||
mux_clk = clk_register(NULL, &frac_mux->hw);
|
||||
if (IS_ERR(mux_clk)) {
|
||||
kfree(frac);
|
||||
return clk;
|
||||
return mux_clk;
|
||||
}
|
||||
|
||||
rockchip_clk_add_lookup(ctx, mux_clk, child->id);
|
||||
|
@ -301,7 +299,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
|||
if (frac->mux_frac_idx >= 0) {
|
||||
pr_debug("%s: found fractional parent in mux at pos %d\n",
|
||||
__func__, frac->mux_frac_idx);
|
||||
ret = clk_notifier_register(clk, &frac->clk_nb);
|
||||
ret = clk_notifier_register(hw->clk, &frac->clk_nb);
|
||||
if (ret)
|
||||
pr_err("%s: failed to register clock notifier for %s\n",
|
||||
__func__, name);
|
||||
|
@ -311,7 +309,7 @@ static struct clk *rockchip_clk_register_frac_branch(
|
|||
}
|
||||
}
|
||||
|
||||
return clk;
|
||||
return hw->clk;
|
||||
}
|
||||
|
||||
static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
||||
|
@ -320,7 +318,7 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
|||
int gate_offset, u8 gate_shift, u8 gate_flags,
|
||||
unsigned long flags, spinlock_t *lock)
|
||||
{
|
||||
struct clk *clk;
|
||||
struct clk_hw *hw;
|
||||
struct clk_gate *gate = NULL;
|
||||
struct clk_fixed_factor *fix = NULL;
|
||||
|
||||
|
@ -349,20 +347,22 @@ static struct clk *rockchip_clk_register_factor_branch(const char *name,
|
|||
fix->mult = mult;
|
||||
fix->div = div;
|
||||
|
||||
clk = clk_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&fix->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(clk)) {
|
||||
hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
|
||||
NULL, NULL,
|
||||
&fix->hw, &clk_fixed_factor_ops,
|
||||
&gate->hw, &clk_gate_ops, flags);
|
||||
if (IS_ERR(hw)) {
|
||||
kfree(fix);
|
||||
kfree(gate);
|
||||
return ERR_CAST(hw);
|
||||
}
|
||||
|
||||
return clk;
|
||||
return hw->clk;
|
||||
}
|
||||
|
||||
struct rockchip_clk_provider * __init rockchip_clk_init(struct device_node *np,
|
||||
void __iomem *base, unsigned long nr_clks)
|
||||
struct rockchip_clk_provider *rockchip_clk_init(struct device_node *np,
|
||||
void __iomem *base,
|
||||
unsigned long nr_clks)
|
||||
{
|
||||
struct rockchip_clk_provider *ctx;
|
||||
struct clk **clk_table;
|
||||
|
@ -394,14 +394,16 @@ err_free:
|
|||
kfree(ctx);
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_init);
|
||||
|
||||
void __init rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx)
|
||||
void rockchip_clk_of_add_provider(struct device_node *np,
|
||||
struct rockchip_clk_provider *ctx)
|
||||
{
|
||||
if (of_clk_add_provider(np, of_clk_src_onecell_get,
|
||||
&ctx->clk_data))
|
||||
pr_err("%s: could not register clk provider\n", __func__);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
|
||||
|
||||
void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
||||
struct clk *clk, unsigned int id)
|
||||
|
@ -409,8 +411,9 @@ void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
|
|||
if (ctx->clk_data.clks && id)
|
||||
ctx->clk_data.clks[id] = clk;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
|
||||
|
||||
void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_pll_clock *list,
|
||||
unsigned int nr_pll, int grf_lock_offset)
|
||||
{
|
||||
|
@ -433,11 +436,11 @@ void __init rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
|
|||
rockchip_clk_add_lookup(ctx, clk, list->id);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_plls);
|
||||
|
||||
void __init rockchip_clk_register_branches(
|
||||
struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
|
||||
struct rockchip_clk_branch *list,
|
||||
unsigned int nr_clk)
|
||||
{
|
||||
struct clk *clk = NULL;
|
||||
unsigned int idx;
|
||||
|
@ -566,14 +569,15 @@ void __init rockchip_clk_register_branches(
|
|||
rockchip_clk_add_lookup(ctx, clk, list->id);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_branches);
|
||||
|
||||
void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
unsigned int lookup_id,
|
||||
const char *name, const char *const *parent_names,
|
||||
u8 num_parents,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data,
|
||||
const struct rockchip_cpuclk_rate_table *rates,
|
||||
int nrates)
|
||||
void rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
||||
unsigned int lookup_id,
|
||||
const char *name, const char *const *parent_names,
|
||||
u8 num_parents,
|
||||
const struct rockchip_cpuclk_reg_data *reg_data,
|
||||
const struct rockchip_cpuclk_rate_table *rates,
|
||||
int nrates)
|
||||
{
|
||||
struct clk *clk;
|
||||
|
||||
|
@ -588,9 +592,10 @@ void __init rockchip_clk_register_armclk(struct rockchip_clk_provider *ctx,
|
|||
|
||||
rockchip_clk_add_lookup(ctx, clk, lookup_id);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_register_armclk);
|
||||
|
||||
void __init rockchip_clk_protect_critical(const char *const clocks[],
|
||||
int nclocks)
|
||||
void rockchip_clk_protect_critical(const char *const clocks[],
|
||||
int nclocks)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -602,6 +607,7 @@ void __init rockchip_clk_protect_critical(const char *const clocks[],
|
|||
clk_prepare_enable(clk);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_clk_protect_critical);
|
||||
|
||||
static void __iomem *rst_base;
|
||||
static unsigned int reg_restart;
|
||||
|
@ -621,10 +627,10 @@ static struct notifier_block rockchip_restart_handler = {
|
|||
.priority = 128,
|
||||
};
|
||||
|
||||
void __init
|
||||
void
|
||||
rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
||||
unsigned int reg,
|
||||
void (*cb)(void))
|
||||
unsigned int reg,
|
||||
void (*cb)(void))
|
||||
{
|
||||
int ret;
|
||||
|
||||
|
@ -636,3 +642,4 @@ rockchip_register_restart_notifier(struct rockchip_clk_provider *ctx,
|
|||
pr_err("%s: cannot register restart handler, %d\n",
|
||||
__func__, ret);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_register_restart_notifier);
|
||||
|
|
|
@ -77,9 +77,9 @@ static const struct reset_control_ops rockchip_softrst_ops = {
|
|||
.deassert = rockchip_softrst_deassert,
|
||||
};
|
||||
|
||||
void __init rockchip_register_softrst(struct device_node *np,
|
||||
unsigned int num_regs,
|
||||
void __iomem *base, u8 flags)
|
||||
void rockchip_register_softrst(struct device_node *np,
|
||||
unsigned int num_regs,
|
||||
void __iomem *base, u8 flags)
|
||||
{
|
||||
struct rockchip_softrst *softrst;
|
||||
int ret;
|
||||
|
@ -107,3 +107,4 @@ void __init rockchip_register_softrst(struct device_node *np,
|
|||
kfree(softrst);
|
||||
}
|
||||
};
|
||||
EXPORT_SYMBOL_GPL(rockchip_register_softrst);
|
||||
|
|
Loading…
Reference in New Issue