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arm64/kernel: enable A53 erratum #8434319 handling at runtime 

Omit patching of ADRP instruction at module load time if the current
CPUs are not susceptible to the erratum.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[will: Drop duplicate initialisation of .def_scope field]
Signed-off-by: Will Deacon <will.deacon@arm.com>
hifive-unleashed-5.1
Ard Biesheuvel 2018-03-06 17:15:35 +00:00 committed by Will Deacon
parent e8002e02ab
commit ca79acca27
4 changed files with 14 additions and 2 deletions
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3
arch/arm64/include/asm/cpucaps.h
View File

@ -45,7 +45,8 @@
#define ARM64_HARDEN_BRANCH_PREDICTOR 24
#define ARM64_HARDEN_BP_POST_GUEST_EXIT 25
#define ARM64_HAS_RAS_EXTN 26
#define ARM64_WORKAROUND_843419 27
#define ARM64_NCAPS 27
#define ARM64_NCAPS 28
#endif /* __ASM_CPUCAPS_H */

9
arch/arm64/kernel/cpu_errata.c
View File

@ -298,6 +298,15 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
MIDR_CPU_VAR_REV(1, 2)),
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_843419
{
/* Cortex-A53 r0p[01234] */
.desc = "ARM erratum 843419",
.capability = ARM64_WORKAROUND_843419,
MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),
MIDR_FIXED(0x4, BIT(8)),
},
#endif
#ifdef CONFIG_ARM64_ERRATUM_845719
{
/* Cortex-A53 r0p[01234] */

3
arch/arm64/kernel/module-plts.c
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@ -158,7 +158,8 @@ static unsigned int count_plts(Elf64_Sym *syms, Elf64_Rela *rela, int num,
break;
case R_AARCH64_ADR_PREL_PG_HI21_NC:
case R_AARCH64_ADR_PREL_PG_HI21:
if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419))
if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
!cpus_have_const_cap(ARM64_WORKAROUND_843419))
break;
/*

1
arch/arm64/kernel/module.c
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@ -203,6 +203,7 @@ static int reloc_insn_adrp(struct module *mod, __le32 *place, u64 val)
u32 insn;
if (!IS_ENABLED(CONFIG_ARM64_ERRATUM_843419) ||
!cpus_have_const_cap(ARM64_WORKAROUND_843419) ||
((u64)place & 0xfff) < 0xff8)
return reloc_insn_imm(RELOC_OP_PAGE, place, val, 12, 21,
AARCH64_INSN_IMM_ADR);