ARM: shmobile: bockw: add SDHI0 support
This patch is directly accessing to PUPR4 register which can control SDHI0 CD/WP pin pull-up setting. It should be replaced in the future. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -18,6 +18,8 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/mfd/tmio.h>
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#include <linux/mmc/host.h>
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#include <linux/pinctrl/machine.h>
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#include <linux/platform_device.h>
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#include <linux/regulator/fixed.h>
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@ -54,16 +56,28 @@ static struct resource smsc911x_resources[] = {
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DEFINE_RES_IRQ(irq_pin(0)), /* IRQ 0 */
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};
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/* SDHI */
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static struct sh_mobile_sdhi_info sdhi0_info = {
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.tmio_caps = MMC_CAP_SD_HIGHSPEED,
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.tmio_ocr_mask = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
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.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT,
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};
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static const struct pinctrl_map bockw_pinctrl_map[] = {
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/* SCIF0 */
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PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
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"scif0_data_a", "scif0"),
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PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-r8a7778",
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"scif0_ctrl", "scif0"),
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/* SDHI0 */
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PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7778",
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"sdhi0", "sdhi0"),
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};
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#define FPGA 0x18200000
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#define IRQ0MR 0x30
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#define PFC 0xfffc0000
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#define PUPR4 0x110
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static void __init bockw_init(void)
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{
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void __iomem *base;
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@ -76,6 +90,7 @@ static void __init bockw_init(void)
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ARRAY_SIZE(bockw_pinctrl_map));
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r8a7778_pinmux_init();
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/* for SMSC */
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base = ioremap_nocache(FPGA, SZ_1M);
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if (base) {
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/*
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@ -98,6 +113,20 @@ static void __init bockw_init(void)
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smsc911x_resources, ARRAY_SIZE(smsc911x_resources),
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&smsc911x_data, sizeof(smsc911x_data));
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}
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/* for SDHI */
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base = ioremap_nocache(PFC, 0x200);
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if (base) {
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/*
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* FIXME
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*
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* SDHI CD/WP pin needs pull-up
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*/
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iowrite32(ioread32(base + PUPR4) | (3 << 26), base + PUPR4);
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iounmap(base);
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r8a7778_sdhi_init(0, &sdhi0_info);
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}
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}
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static const char *bockw_boards_compat_dt[] __initdata = {
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