Merge remote-tracking branch 'asoc/fix/ak4642' into asoc-linus
This commit is contained in:
commit
ca89bc248e
|
@ -71,7 +71,7 @@ static int netlink_send(int s, struct cn_msg *msg)
|
|||
nlh->nlmsg_seq = seq++;
|
||||
nlh->nlmsg_pid = getpid();
|
||||
nlh->nlmsg_type = NLMSG_DONE;
|
||||
nlh->nlmsg_len = NLMSG_LENGTH(size - sizeof(*nlh));
|
||||
nlh->nlmsg_len = size;
|
||||
nlh->nlmsg_flags = 0;
|
||||
|
||||
m = NLMSG_DATA(nlh);
|
||||
|
|
86
MAINTAINERS
86
MAINTAINERS
|
@ -1009,6 +1009,7 @@ ARM/Marvell Armada 370 and Armada XP SOC support
|
|||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Gregory Clement <gregory.clement@free-electrons.com>
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-mvebu/
|
||||
|
@ -1016,6 +1017,7 @@ F: arch/arm/mach-mvebu/
|
|||
ARM/Marvell Dove/Kirkwood/MV78xx0/Orion SOC support
|
||||
M: Jason Cooper <jason@lakedaemon.net>
|
||||
M: Andrew Lunn <andrew@lunn.ch>
|
||||
M: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-dove/
|
||||
|
@ -1148,6 +1150,13 @@ F: drivers/net/ethernet/i825xx/ether1*
|
|||
F: drivers/net/ethernet/seeq/ether3*
|
||||
F: drivers/scsi/arm/
|
||||
|
||||
ARM/Rockchip SoC support
|
||||
M: Heiko Stuebner <heiko@sntech.de>
|
||||
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
|
||||
S: Maintained
|
||||
F: arch/arm/mach-rockchip/
|
||||
F: drivers/*/*rockchip*
|
||||
|
||||
ARM/SHARK MACHINE SUPPORT
|
||||
M: Alexander Schulz <alex@shark-linux.de>
|
||||
W: http://www.shark-linux.de/shark.html
|
||||
|
@ -1791,6 +1800,7 @@ F: include/net/bluetooth/
|
|||
|
||||
BONDING DRIVER
|
||||
M: Jay Vosburgh <fubar@us.ibm.com>
|
||||
M: Veaceslav Falico <vfalico@redhat.com>
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
W: http://sourceforge.net/projects/bonding/
|
||||
|
@ -2718,6 +2728,8 @@ T: git git://git.linaro.org/people/sumitsemwal/linux-dma-buf.git
|
|||
DMA GENERIC OFFLOAD ENGINE SUBSYSTEM
|
||||
M: Vinod Koul <vinod.koul@intel.com>
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
L: dmaengine@vger.kernel.org
|
||||
Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
|
||||
S: Supported
|
||||
F: drivers/dma/
|
||||
F: include/linux/dma*
|
||||
|
@ -2821,7 +2833,7 @@ M: Terje Bergström <tbergstrom@nvidia.com>
|
|||
L: dri-devel@lists.freedesktop.org
|
||||
L: linux-tegra@vger.kernel.org
|
||||
T: git git://anongit.freedesktop.org/tegra/linux.git
|
||||
S: Maintained
|
||||
S: Supported
|
||||
F: drivers/gpu/host1x/
|
||||
F: include/uapi/drm/tegra_drm.h
|
||||
F: Documentation/devicetree/bindings/gpu/nvidia,tegra20-host1x.txt
|
||||
|
@ -4357,7 +4369,10 @@ F: arch/x86/kernel/microcode_intel.c
|
|||
|
||||
INTEL I/OAT DMA DRIVER
|
||||
M: Dan Williams <dan.j.williams@intel.com>
|
||||
S: Maintained
|
||||
M: Dave Jiang <dave.jiang@intel.com>
|
||||
L: dmaengine@vger.kernel.org
|
||||
Q: https://patchwork.kernel.org/project/linux-dmaengine/list/
|
||||
S: Supported
|
||||
F: drivers/dma/ioat*
|
||||
|
||||
INTEL IOMMU (VT-d)
|
||||
|
@ -7822,6 +7837,13 @@ F: Documentation/sound/alsa/soc/
|
|||
F: sound/soc/
|
||||
F: include/sound/soc*
|
||||
|
||||
SOUND - DMAENGINE HELPERS
|
||||
M: Lars-Peter Clausen <lars@metafoo.de>
|
||||
S: Supported
|
||||
F: include/sound/dmaengine_pcm.h
|
||||
F: sound/core/pcm_dmaengine.c
|
||||
F: sound/soc/soc-generic-dmaengine-pcm.c
|
||||
|
||||
SPARC + UltraSPARC (sparc/sparc64)
|
||||
M: "David S. Miller" <davem@davemloft.net>
|
||||
L: sparclinux@vger.kernel.org
|
||||
|
@ -8294,14 +8316,72 @@ L: linux-media@vger.kernel.org
|
|||
S: Maintained
|
||||
F: drivers/media/rc/ttusbir.c
|
||||
|
||||
TEGRA SUPPORT
|
||||
TEGRA ARCHITECTURE SUPPORT
|
||||
M: Stephen Warren <swarren@wwwdotorg.org>
|
||||
M: Thierry Reding <thierry.reding@gmail.com>
|
||||
L: linux-tegra@vger.kernel.org
|
||||
Q: http://patchwork.ozlabs.org/project/linux-tegra/list/
|
||||
T: git git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra.git
|
||||
S: Supported
|
||||
N: [^a-z]tegra
|
||||
|
||||
TEGRA ASOC DRIVER
|
||||
M: Stephen Warren <swarren@wwwdotorg.org>
|
||||
S: Supported
|
||||
F: sound/soc/tegra/
|
||||
|
||||
TEGRA CLOCK DRIVER
|
||||
M: Peter De Schrijver <pdeschrijver@nvidia.com>
|
||||
M: Prashant Gaikwad <pgaikwad@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/clk/tegra/
|
||||
|
||||
TEGRA DMA DRIVER
|
||||
M: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/dma/tegra20-apb-dma.c
|
||||
|
||||
TEGRA GPIO DRIVER
|
||||
M: Stephen Warren <swarren@wwwdotorg.org>
|
||||
S: Supported
|
||||
F: drivers/gpio/gpio-tegra.c
|
||||
|
||||
TEGRA I2C DRIVER
|
||||
M: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/i2c/busses/i2c-tegra.c
|
||||
|
||||
TEGRA IOMMU DRIVERS
|
||||
M: Hiroshi Doyu <hdoyu@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/iommu/tegra*
|
||||
|
||||
TEGRA KBC DRIVER
|
||||
M: Rakesh Iyer <riyer@nvidia.com>
|
||||
M: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/input/keyboard/tegra-kbc.c
|
||||
|
||||
TEGRA PINCTRL DRIVER
|
||||
M: Stephen Warren <swarren@wwwdotorg.org>
|
||||
S: Supported
|
||||
F: drivers/pinctrl/pinctrl-tegra*
|
||||
|
||||
TEGRA PWM DRIVER
|
||||
M: Thierry Reding <thierry.reding@gmail.com>
|
||||
S: Supported
|
||||
F: drivers/pwm/pwm-tegra.c
|
||||
|
||||
TEGRA SERIAL DRIVER
|
||||
M: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/tty/serial/serial-tegra.c
|
||||
|
||||
TEGRA SPI DRIVER
|
||||
M: Laxman Dewangan <ldewangan@nvidia.com>
|
||||
S: Supported
|
||||
F: drivers/spi/spi-tegra*
|
||||
|
||||
TEHUTI ETHERNET DRIVER
|
||||
M: Andy Gospodarek <andy@greyhouse.net>
|
||||
L: netdev@vger.kernel.org
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 12
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc6
|
||||
EXTRAVERSION = -rc7
|
||||
NAME = One Giant Leap for Frogkind
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -9,11 +9,6 @@
|
|||
model = "ARM Integrator/CP";
|
||||
compatible = "arm,integrator-cp";
|
||||
|
||||
aliases {
|
||||
arm,timer-primary = &timer2;
|
||||
arm,timer-secondary = &timer1;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
|
||||
};
|
||||
|
@ -24,14 +19,18 @@
|
|||
};
|
||||
|
||||
timer0: timer@13000000 {
|
||||
/* TIMER0 runs @ 25MHz */
|
||||
compatible = "arm,integrator-cp-timer";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer1: timer@13000100 {
|
||||
/* TIMER1 runs @ 1MHz */
|
||||
compatible = "arm,integrator-cp-timer";
|
||||
};
|
||||
|
||||
timer2: timer@13000200 {
|
||||
/* TIMER2 runs @ 1MHz */
|
||||
compatible = "arm,integrator-cp-timer";
|
||||
};
|
||||
|
||||
|
|
|
@ -930,4 +930,5 @@ void bpf_jit_free(struct sk_filter *fp)
|
|||
{
|
||||
if (fp->bpf_func != sk_run_filter)
|
||||
module_free(NULL, fp->bpf_func);
|
||||
kfree(fp);
|
||||
}
|
||||
|
|
|
@ -40,6 +40,8 @@ CONFIG_IP_NF_QUEUE=m
|
|||
CONFIG_LLC2=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_PARPORT=y
|
||||
|
|
|
@ -79,6 +79,8 @@ CONFIG_IP_DCCP=m
|
|||
CONFIG_LLC2=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_BLK_DEV_UMEM=m
|
||||
|
|
|
@ -4,6 +4,7 @@ CONFIG_IKCONFIG=y
|
|||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
|
@ -27,6 +28,8 @@ CONFIG_IP_PNP_BOOTP=y
|
|||
# CONFIG_INET_LRO is not set
|
||||
CONFIG_IPV6=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_PARPORT=y
|
||||
CONFIG_PARPORT_PC=y
|
||||
|
|
|
@ -5,6 +5,7 @@ CONFIG_IKCONFIG=y
|
|||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=16
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EXPERT=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
|
@ -39,6 +40,8 @@ CONFIG_NETFILTER_DEBUG=y
|
|||
CONFIG_IP_NF_QUEUE=m
|
||||
CONFIG_NET_PKTGEN=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_BLK_DEV_UMEM=m
|
||||
|
|
|
@ -62,6 +62,8 @@ CONFIG_TIPC=m
|
|||
CONFIG_LLC2=m
|
||||
CONFIG_DNS_RESOLVER=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
CONFIG_PARPORT=y
|
||||
CONFIG_PARPORT_PC=y
|
||||
|
|
|
@ -49,6 +49,8 @@ CONFIG_INET6_ESP=y
|
|||
CONFIG_INET6_IPCOMP=y
|
||||
CONFIG_LLC2=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_DEVTMPFS_MOUNT=y
|
||||
# CONFIG_STANDALONE is not set
|
||||
# CONFIG_PREVENT_FIRMWARE_BUILD is not set
|
||||
CONFIG_PARPORT=y
|
||||
|
|
|
@ -602,7 +602,6 @@ flush_cache_page(struct vm_area_struct *vma, unsigned long vmaddr, unsigned long
|
|||
__flush_cache_page(vma, vmaddr, PFN_PHYS(pfn));
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(flush_cache_page);
|
||||
|
||||
#ifdef CONFIG_PARISC_TMPALIAS
|
||||
|
||||
|
|
|
@ -195,6 +195,8 @@ common_stext:
|
|||
ldw MEM_PDC_HI(%r0),%r6
|
||||
depd %r6, 31, 32, %r3 /* move to upper word */
|
||||
|
||||
mfctl %cr30,%r6 /* PCX-W2 firmware bug */
|
||||
|
||||
ldo PDC_PSW(%r0),%arg0 /* 21 */
|
||||
ldo PDC_PSW_SET_DEFAULTS(%r0),%arg1 /* 2 */
|
||||
ldo PDC_PSW_WIDE_BIT(%r0),%arg2 /* 2 */
|
||||
|
@ -203,6 +205,8 @@ common_stext:
|
|||
copy %r0,%arg3
|
||||
|
||||
stext_pdc_ret:
|
||||
mtctl %r6,%cr30 /* restore task thread info */
|
||||
|
||||
/* restore rfi target address*/
|
||||
ldd TI_TASK-THREAD_SZ_ALGN(%sp), %r10
|
||||
tophys_r1 %r10
|
||||
|
|
|
@ -691,4 +691,5 @@ void bpf_jit_free(struct sk_filter *fp)
|
|||
{
|
||||
if (fp->bpf_func != sk_run_filter)
|
||||
module_free(NULL, fp->bpf_func);
|
||||
kfree(fp);
|
||||
}
|
||||
|
|
|
@ -748,7 +748,9 @@ static inline void pgste_set_key(pte_t *ptep, pgste_t pgste, pte_t entry)
|
|||
|
||||
static inline void pgste_set_pte(pte_t *ptep, pte_t entry)
|
||||
{
|
||||
if (!MACHINE_HAS_ESOP && (pte_val(entry) & _PAGE_WRITE)) {
|
||||
if (!MACHINE_HAS_ESOP &&
|
||||
(pte_val(entry) & _PAGE_PRESENT) &&
|
||||
(pte_val(entry) & _PAGE_WRITE)) {
|
||||
/*
|
||||
* Without enhanced suppression-on-protection force
|
||||
* the dirty bit on for all writable ptes.
|
||||
|
|
|
@ -71,30 +71,30 @@ static inline void local_tick_enable(unsigned long long comp)
|
|||
|
||||
typedef unsigned long long cycles_t;
|
||||
|
||||
static inline unsigned long long get_tod_clock(void)
|
||||
{
|
||||
unsigned long long clk;
|
||||
|
||||
#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
|
||||
asm volatile(".insn s,0xb27c0000,%0" : "=Q" (clk) : : "cc");
|
||||
#else
|
||||
asm volatile("stck %0" : "=Q" (clk) : : "cc");
|
||||
#endif
|
||||
return clk;
|
||||
}
|
||||
|
||||
static inline void get_tod_clock_ext(char *clk)
|
||||
{
|
||||
asm volatile("stcke %0" : "=Q" (*clk) : : "cc");
|
||||
}
|
||||
|
||||
static inline unsigned long long get_tod_clock_xt(void)
|
||||
static inline unsigned long long get_tod_clock(void)
|
||||
{
|
||||
unsigned char clk[16];
|
||||
get_tod_clock_ext(clk);
|
||||
return *((unsigned long long *)&clk[1]);
|
||||
}
|
||||
|
||||
static inline unsigned long long get_tod_clock_fast(void)
|
||||
{
|
||||
#ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
|
||||
unsigned long long clk;
|
||||
|
||||
asm volatile("stckf %0" : "=Q" (clk) : : "cc");
|
||||
return clk;
|
||||
#else
|
||||
return get_tod_clock();
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline cycles_t get_cycles(void)
|
||||
{
|
||||
return (cycles_t) get_tod_clock() >> 2;
|
||||
|
@ -125,7 +125,7 @@ extern u64 sched_clock_base_cc;
|
|||
*/
|
||||
static inline unsigned long long get_tod_clock_monotonic(void)
|
||||
{
|
||||
return get_tod_clock_xt() - sched_clock_base_cc;
|
||||
return get_tod_clock() - sched_clock_base_cc;
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
@ -99,7 +99,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, siginfo_t *from)
|
|||
break;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
return err ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
|
||||
|
@ -148,7 +148,7 @@ int copy_siginfo_from_user32(siginfo_t *to, compat_siginfo_t __user *from)
|
|||
break;
|
||||
}
|
||||
}
|
||||
return err;
|
||||
return err ? -EFAULT : 0;
|
||||
}
|
||||
|
||||
static int save_sigregs32(struct pt_regs *regs, _sigregs32 __user *sregs)
|
||||
|
|
|
@ -867,7 +867,7 @@ static inline void
|
|||
debug_finish_entry(debug_info_t * id, debug_entry_t* active, int level,
|
||||
int exception)
|
||||
{
|
||||
active->id.stck = get_tod_clock();
|
||||
active->id.stck = get_tod_clock_fast();
|
||||
active->id.fields.cpuid = smp_processor_id();
|
||||
active->caller = __builtin_return_address(0);
|
||||
active->id.fields.exception = exception;
|
||||
|
|
|
@ -385,7 +385,7 @@ static int kvm_cpu_has_interrupt(struct kvm_vcpu *vcpu)
|
|||
}
|
||||
|
||||
if ((!rc) && (vcpu->arch.sie_block->ckc <
|
||||
get_tod_clock() + vcpu->arch.sie_block->epoch)) {
|
||||
get_tod_clock_fast() + vcpu->arch.sie_block->epoch)) {
|
||||
if ((!psw_extint_disabled(vcpu)) &&
|
||||
(vcpu->arch.sie_block->gcr[0] & 0x800ul))
|
||||
rc = 1;
|
||||
|
@ -425,7 +425,7 @@ int kvm_s390_handle_wait(struct kvm_vcpu *vcpu)
|
|||
goto no_timer;
|
||||
}
|
||||
|
||||
now = get_tod_clock() + vcpu->arch.sie_block->epoch;
|
||||
now = get_tod_clock_fast() + vcpu->arch.sie_block->epoch;
|
||||
if (vcpu->arch.sie_block->ckc < now) {
|
||||
__unset_cpu_idle(vcpu);
|
||||
return 0;
|
||||
|
@ -515,7 +515,7 @@ void kvm_s390_deliver_pending_interrupts(struct kvm_vcpu *vcpu)
|
|||
}
|
||||
|
||||
if ((vcpu->arch.sie_block->ckc <
|
||||
get_tod_clock() + vcpu->arch.sie_block->epoch))
|
||||
get_tod_clock_fast() + vcpu->arch.sie_block->epoch))
|
||||
__try_deliver_ckc_interrupt(vcpu);
|
||||
|
||||
if (atomic_read(&fi->active)) {
|
||||
|
|
|
@ -44,7 +44,7 @@ static void __udelay_disabled(unsigned long long usecs)
|
|||
do {
|
||||
set_clock_comparator(end);
|
||||
vtime_stop_cpu();
|
||||
} while (get_tod_clock() < end);
|
||||
} while (get_tod_clock_fast() < end);
|
||||
lockdep_on();
|
||||
__ctl_load(cr0, 0, 0);
|
||||
__ctl_load(cr6, 6, 6);
|
||||
|
@ -55,7 +55,7 @@ static void __udelay_enabled(unsigned long long usecs)
|
|||
{
|
||||
u64 clock_saved, end;
|
||||
|
||||
end = get_tod_clock() + (usecs << 12);
|
||||
end = get_tod_clock_fast() + (usecs << 12);
|
||||
do {
|
||||
clock_saved = 0;
|
||||
if (end < S390_lowcore.clock_comparator) {
|
||||
|
@ -65,7 +65,7 @@ static void __udelay_enabled(unsigned long long usecs)
|
|||
vtime_stop_cpu();
|
||||
if (clock_saved)
|
||||
local_tick_enable(clock_saved);
|
||||
} while (get_tod_clock() < end);
|
||||
} while (get_tod_clock_fast() < end);
|
||||
}
|
||||
|
||||
/*
|
||||
|
@ -109,8 +109,8 @@ void udelay_simple(unsigned long long usecs)
|
|||
{
|
||||
u64 end;
|
||||
|
||||
end = get_tod_clock() + (usecs << 12);
|
||||
while (get_tod_clock() < end)
|
||||
end = get_tod_clock_fast() + (usecs << 12);
|
||||
while (get_tod_clock_fast() < end)
|
||||
cpu_relax();
|
||||
}
|
||||
|
||||
|
@ -120,10 +120,10 @@ void __ndelay(unsigned long long nsecs)
|
|||
|
||||
nsecs <<= 9;
|
||||
do_div(nsecs, 125);
|
||||
end = get_tod_clock() + nsecs;
|
||||
end = get_tod_clock_fast() + nsecs;
|
||||
if (nsecs & ~0xfffUL)
|
||||
__udelay(nsecs >> 12);
|
||||
while (get_tod_clock() < end)
|
||||
while (get_tod_clock_fast() < end)
|
||||
barrier();
|
||||
}
|
||||
EXPORT_SYMBOL(__ndelay);
|
||||
|
|
|
@ -881,7 +881,9 @@ void bpf_jit_free(struct sk_filter *fp)
|
|||
struct bpf_binary_header *header = (void *)addr;
|
||||
|
||||
if (fp->bpf_func == sk_run_filter)
|
||||
return;
|
||||
goto free_filter;
|
||||
set_memory_rw(addr, header->pages);
|
||||
module_free(NULL, header);
|
||||
free_filter:
|
||||
kfree(fp);
|
||||
}
|
||||
|
|
|
@ -808,4 +808,5 @@ void bpf_jit_free(struct sk_filter *fp)
|
|||
{
|
||||
if (fp->bpf_func != sk_run_filter)
|
||||
module_free(NULL, fp->bpf_func);
|
||||
kfree(fp);
|
||||
}
|
||||
|
|
|
@ -772,13 +772,21 @@ out:
|
|||
return;
|
||||
}
|
||||
|
||||
static void bpf_jit_free_deferred(struct work_struct *work)
|
||||
{
|
||||
struct sk_filter *fp = container_of(work, struct sk_filter, work);
|
||||
unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
|
||||
struct bpf_binary_header *header = (void *)addr;
|
||||
|
||||
set_memory_rw(addr, header->pages);
|
||||
module_free(NULL, header);
|
||||
kfree(fp);
|
||||
}
|
||||
|
||||
void bpf_jit_free(struct sk_filter *fp)
|
||||
{
|
||||
if (fp->bpf_func != sk_run_filter) {
|
||||
unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
|
||||
struct bpf_binary_header *header = (void *)addr;
|
||||
|
||||
set_memory_rw(addr, header->pages);
|
||||
module_free(NULL, header);
|
||||
INIT_WORK(&fp->work, bpf_jit_free_deferred);
|
||||
schedule_work(&fp->work);
|
||||
}
|
||||
}
|
||||
|
|
|
@ -1343,7 +1343,7 @@ static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
|
|||
if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
|
||||
host->flags |= ATA_HOST_PARALLEL_SCAN;
|
||||
else
|
||||
printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
|
||||
dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
|
||||
|
||||
if (pi.flags & ATA_FLAG_EM)
|
||||
ahci_reset_em(host);
|
||||
|
|
|
@ -184,7 +184,7 @@ static int ahci_probe(struct platform_device *pdev)
|
|||
if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
|
||||
host->flags |= ATA_HOST_PARALLEL_SCAN;
|
||||
else
|
||||
printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
|
||||
dev_info(dev, "SSS flag set, parallel bus scan disabled\n");
|
||||
|
||||
if (pi.flags & ATA_FLAG_EM)
|
||||
ahci_reset_em(host);
|
||||
|
|
|
@ -778,8 +778,16 @@ static void ahci_start_port(struct ata_port *ap)
|
|||
rc = ap->ops->transmit_led_message(ap,
|
||||
emp->led_state,
|
||||
4);
|
||||
/*
|
||||
* If busy, give a breather but do not
|
||||
* release EH ownership by using msleep()
|
||||
* instead of ata_msleep(). EM Transmit
|
||||
* bit is busy for the whole host and
|
||||
* releasing ownership will cause other
|
||||
* ports to fail the same way.
|
||||
*/
|
||||
if (rc == -EBUSY)
|
||||
ata_msleep(ap, 1);
|
||||
msleep(1);
|
||||
else
|
||||
break;
|
||||
}
|
||||
|
|
|
@ -1322,14 +1322,14 @@ void ata_eh_qc_complete(struct ata_queued_cmd *qc)
|
|||
* should be retried. To be used from EH.
|
||||
*
|
||||
* SCSI midlayer limits the number of retries to scmd->allowed.
|
||||
* scmd->retries is decremented for commands which get retried
|
||||
* scmd->allowed is incremented for commands which get retried
|
||||
* due to unrelated failures (qc->err_mask is zero).
|
||||
*/
|
||||
void ata_eh_qc_retry(struct ata_queued_cmd *qc)
|
||||
{
|
||||
struct scsi_cmnd *scmd = qc->scsicmd;
|
||||
if (!qc->err_mask && scmd->retries)
|
||||
scmd->retries--;
|
||||
if (!qc->err_mask)
|
||||
scmd->allowed++;
|
||||
__ata_eh_qc_complete(qc);
|
||||
}
|
||||
|
||||
|
|
|
@ -78,7 +78,7 @@ static int isapnp_init_one(struct pnp_dev *idev, const struct pnp_device_id *dev
|
|||
|
||||
ap->ioaddr.cmd_addr = cmd_addr;
|
||||
|
||||
if (pnp_port_valid(idev, 1) == 0) {
|
||||
if (pnp_port_valid(idev, 1)) {
|
||||
ctl_addr = devm_ioport_map(&idev->dev,
|
||||
pnp_port_start(idev, 1), 1);
|
||||
ap->ioaddr.altstatus_addr = ctl_addr;
|
||||
|
|
|
@ -65,6 +65,7 @@ void proc_fork_connector(struct task_struct *task)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -80,6 +81,7 @@ void proc_fork_connector(struct task_struct *task)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
/* If cn_netlink_send() failed, the data is not sent */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
@ -96,6 +98,7 @@ void proc_exec_connector(struct task_struct *task)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -106,6 +109,7 @@ void proc_exec_connector(struct task_struct *task)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -122,6 +126,7 @@ void proc_id_connector(struct task_struct *task, int which_id)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
ev->what = which_id;
|
||||
ev->event_data.id.process_pid = task->pid;
|
||||
ev->event_data.id.process_tgid = task->tgid;
|
||||
|
@ -145,6 +150,7 @@ void proc_id_connector(struct task_struct *task, int which_id)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -160,6 +166,7 @@ void proc_sid_connector(struct task_struct *task)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -170,6 +177,7 @@ void proc_sid_connector(struct task_struct *task)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -185,6 +193,7 @@ void proc_ptrace_connector(struct task_struct *task, int ptrace_id)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -203,6 +212,7 @@ void proc_ptrace_connector(struct task_struct *task, int ptrace_id)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -218,6 +228,7 @@ void proc_comm_connector(struct task_struct *task)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -229,6 +240,7 @@ void proc_comm_connector(struct task_struct *task)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -244,6 +256,7 @@ void proc_coredump_connector(struct task_struct *task)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -254,6 +267,7 @@ void proc_coredump_connector(struct task_struct *task)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -269,6 +283,7 @@ void proc_exit_connector(struct task_struct *task)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
get_seq(&msg->seq, &ev->cpu);
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -281,6 +296,7 @@ void proc_exit_connector(struct task_struct *task)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = 0; /* not used */
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
@ -304,6 +320,7 @@ static void cn_proc_ack(int err, int rcvd_seq, int rcvd_ack)
|
|||
|
||||
msg = (struct cn_msg *)buffer;
|
||||
ev = (struct proc_event *)msg->data;
|
||||
memset(&ev->event_data, 0, sizeof(ev->event_data));
|
||||
msg->seq = rcvd_seq;
|
||||
ktime_get_ts(&ts); /* get high res monotonic timestamp */
|
||||
put_unaligned(timespec_to_ns(&ts), (__u64 *)&ev->timestamp_ns);
|
||||
|
@ -313,6 +330,7 @@ static void cn_proc_ack(int err, int rcvd_seq, int rcvd_ack)
|
|||
memcpy(&msg->id, &cn_proc_event_id, sizeof(msg->id));
|
||||
msg->ack = rcvd_ack + 1;
|
||||
msg->len = sizeof(*ev);
|
||||
msg->flags = 0; /* not used */
|
||||
cn_netlink_send(msg, CN_IDX_PROC, GFP_KERNEL);
|
||||
}
|
||||
|
||||
|
|
|
@ -109,7 +109,7 @@ int cn_netlink_send(struct cn_msg *msg, u32 __group, gfp_t gfp_mask)
|
|||
|
||||
data = nlmsg_data(nlh);
|
||||
|
||||
memcpy(data, msg, sizeof(*data) + msg->len);
|
||||
memcpy(data, msg, size);
|
||||
|
||||
NETLINK_CB(skb).dst_group = group;
|
||||
|
||||
|
@ -157,17 +157,18 @@ static int cn_call_callback(struct sk_buff *skb)
|
|||
static void cn_rx_skb(struct sk_buff *__skb)
|
||||
{
|
||||
struct nlmsghdr *nlh;
|
||||
int err;
|
||||
struct sk_buff *skb;
|
||||
int len, err;
|
||||
|
||||
skb = skb_get(__skb);
|
||||
|
||||
if (skb->len >= NLMSG_HDRLEN) {
|
||||
nlh = nlmsg_hdr(skb);
|
||||
len = nlmsg_len(nlh);
|
||||
|
||||
if (nlh->nlmsg_len < sizeof(struct cn_msg) ||
|
||||
if (len < (int)sizeof(struct cn_msg) ||
|
||||
skb->len < nlh->nlmsg_len ||
|
||||
nlh->nlmsg_len > CONNECTOR_MAX_MSG_SIZE) {
|
||||
len > CONNECTOR_MAX_MSG_SIZE) {
|
||||
kfree_skb(skb);
|
||||
return;
|
||||
}
|
||||
|
|
|
@ -986,12 +986,12 @@ static int __init acpi_cpufreq_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
if (acpi_disabled)
|
||||
return -ENODEV;
|
||||
|
||||
/* don't keep reloading if cpufreq_driver exists */
|
||||
if (cpufreq_get_current_driver())
|
||||
return 0;
|
||||
|
||||
if (acpi_disabled)
|
||||
return 0;
|
||||
return -EEXIST;
|
||||
|
||||
pr_debug("acpi_cpufreq_init\n");
|
||||
|
||||
|
|
|
@ -48,7 +48,7 @@ static inline int32_t div_fp(int32_t x, int32_t y)
|
|||
}
|
||||
|
||||
struct sample {
|
||||
int core_pct_busy;
|
||||
int32_t core_pct_busy;
|
||||
u64 aperf;
|
||||
u64 mperf;
|
||||
int freq;
|
||||
|
@ -68,7 +68,7 @@ struct _pid {
|
|||
int32_t i_gain;
|
||||
int32_t d_gain;
|
||||
int deadband;
|
||||
int last_err;
|
||||
int32_t last_err;
|
||||
};
|
||||
|
||||
struct cpudata {
|
||||
|
@ -153,16 +153,15 @@ static inline void pid_d_gain_set(struct _pid *pid, int percent)
|
|||
pid->d_gain = div_fp(int_tofp(percent), int_tofp(100));
|
||||
}
|
||||
|
||||
static signed int pid_calc(struct _pid *pid, int busy)
|
||||
static signed int pid_calc(struct _pid *pid, int32_t busy)
|
||||
{
|
||||
signed int err, result;
|
||||
signed int result;
|
||||
int32_t pterm, dterm, fp_error;
|
||||
int32_t integral_limit;
|
||||
|
||||
err = pid->setpoint - busy;
|
||||
fp_error = int_tofp(err);
|
||||
fp_error = int_tofp(pid->setpoint) - busy;
|
||||
|
||||
if (abs(err) <= pid->deadband)
|
||||
if (abs(fp_error) <= int_tofp(pid->deadband))
|
||||
return 0;
|
||||
|
||||
pterm = mul_fp(pid->p_gain, fp_error);
|
||||
|
@ -176,8 +175,8 @@ static signed int pid_calc(struct _pid *pid, int busy)
|
|||
if (pid->integral < -integral_limit)
|
||||
pid->integral = -integral_limit;
|
||||
|
||||
dterm = mul_fp(pid->d_gain, (err - pid->last_err));
|
||||
pid->last_err = err;
|
||||
dterm = mul_fp(pid->d_gain, fp_error - pid->last_err);
|
||||
pid->last_err = fp_error;
|
||||
|
||||
result = pterm + mul_fp(pid->integral, pid->i_gain) + dterm;
|
||||
|
||||
|
@ -367,12 +366,13 @@ static int intel_pstate_turbo_pstate(void)
|
|||
static void intel_pstate_get_min_max(struct cpudata *cpu, int *min, int *max)
|
||||
{
|
||||
int max_perf = cpu->pstate.turbo_pstate;
|
||||
int max_perf_adj;
|
||||
int min_perf;
|
||||
if (limits.no_turbo)
|
||||
max_perf = cpu->pstate.max_pstate;
|
||||
|
||||
max_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
|
||||
*max = clamp_t(int, max_perf,
|
||||
max_perf_adj = fp_toint(mul_fp(int_tofp(max_perf), limits.max_perf));
|
||||
*max = clamp_t(int, max_perf_adj,
|
||||
cpu->pstate.min_pstate, cpu->pstate.turbo_pstate);
|
||||
|
||||
min_perf = fp_toint(mul_fp(int_tofp(max_perf), limits.min_perf));
|
||||
|
@ -436,8 +436,9 @@ static inline void intel_pstate_calc_busy(struct cpudata *cpu,
|
|||
struct sample *sample)
|
||||
{
|
||||
u64 core_pct;
|
||||
core_pct = div64_u64(sample->aperf * 100, sample->mperf);
|
||||
sample->freq = cpu->pstate.max_pstate * core_pct * 1000;
|
||||
core_pct = div64_u64(int_tofp(sample->aperf * 100),
|
||||
sample->mperf);
|
||||
sample->freq = fp_toint(cpu->pstate.max_pstate * core_pct * 1000);
|
||||
|
||||
sample->core_pct_busy = core_pct;
|
||||
}
|
||||
|
@ -469,22 +470,19 @@ static inline void intel_pstate_set_sample_time(struct cpudata *cpu)
|
|||
mod_timer_pinned(&cpu->timer, jiffies + delay);
|
||||
}
|
||||
|
||||
static inline int intel_pstate_get_scaled_busy(struct cpudata *cpu)
|
||||
static inline int32_t intel_pstate_get_scaled_busy(struct cpudata *cpu)
|
||||
{
|
||||
int32_t busy_scaled;
|
||||
int32_t core_busy, max_pstate, current_pstate;
|
||||
|
||||
core_busy = int_tofp(cpu->samples[cpu->sample_ptr].core_pct_busy);
|
||||
core_busy = cpu->samples[cpu->sample_ptr].core_pct_busy;
|
||||
max_pstate = int_tofp(cpu->pstate.max_pstate);
|
||||
current_pstate = int_tofp(cpu->pstate.current_pstate);
|
||||
busy_scaled = mul_fp(core_busy, div_fp(max_pstate, current_pstate));
|
||||
|
||||
return fp_toint(busy_scaled);
|
||||
return mul_fp(core_busy, div_fp(max_pstate, current_pstate));
|
||||
}
|
||||
|
||||
static inline void intel_pstate_adjust_busy_pstate(struct cpudata *cpu)
|
||||
{
|
||||
int busy_scaled;
|
||||
int32_t busy_scaled;
|
||||
struct _pid *pid;
|
||||
signed int ctl = 0;
|
||||
int steps;
|
||||
|
|
|
@ -305,6 +305,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
|||
edma_alloc_slot(EDMA_CTLR(echan->ch_num),
|
||||
EDMA_SLOT_ANY);
|
||||
if (echan->slot[i] < 0) {
|
||||
kfree(edesc);
|
||||
dev_err(dev, "Failed to allocate slot\n");
|
||||
kfree(edesc);
|
||||
return NULL;
|
||||
|
@ -346,6 +347,7 @@ static struct dma_async_tx_descriptor *edma_prep_slave_sg(
|
|||
ccnt = sg_dma_len(sg) / (acnt * bcnt);
|
||||
if (ccnt > (SZ_64K - 1)) {
|
||||
dev_err(dev, "Exceeded max SG segment size\n");
|
||||
kfree(edesc);
|
||||
return NULL;
|
||||
}
|
||||
cidx = acnt * bcnt;
|
||||
|
|
|
@ -402,9 +402,16 @@ long drm_ioctl(struct file *filp,
|
|||
cmd = ioctl->cmd_drv;
|
||||
}
|
||||
else if ((nr >= DRM_COMMAND_END) || (nr < DRM_COMMAND_BASE)) {
|
||||
u32 drv_size;
|
||||
|
||||
ioctl = &drm_ioctls[nr];
|
||||
cmd = ioctl->cmd;
|
||||
|
||||
drv_size = _IOC_SIZE(ioctl->cmd);
|
||||
usize = asize = _IOC_SIZE(cmd);
|
||||
if (drv_size > asize)
|
||||
asize = drv_size;
|
||||
|
||||
cmd = ioctl->cmd;
|
||||
} else
|
||||
goto err_i1;
|
||||
|
||||
|
|
|
@ -505,6 +505,8 @@ static int i915_drm_freeze(struct drm_device *dev)
|
|||
intel_modeset_suspend_hw(dev);
|
||||
}
|
||||
|
||||
i915_gem_suspend_gtt_mappings(dev);
|
||||
|
||||
i915_save_state(dev);
|
||||
|
||||
intel_opregion_fini(dev);
|
||||
|
@ -648,7 +650,8 @@ static int i915_drm_thaw(struct drm_device *dev)
|
|||
mutex_lock(&dev->struct_mutex);
|
||||
i915_gem_restore_gtt_mappings(dev);
|
||||
mutex_unlock(&dev->struct_mutex);
|
||||
}
|
||||
} else if (drm_core_check_feature(dev, DRIVER_MODESET))
|
||||
i915_check_and_clear_faults(dev);
|
||||
|
||||
__i915_drm_thaw(dev);
|
||||
|
||||
|
|
|
@ -497,10 +497,12 @@ struct i915_address_space {
|
|||
|
||||
/* FIXME: Need a more generic return type */
|
||||
gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr,
|
||||
enum i915_cache_level level);
|
||||
enum i915_cache_level level,
|
||||
bool valid); /* Create a valid PTE */
|
||||
void (*clear_range)(struct i915_address_space *vm,
|
||||
unsigned int first_entry,
|
||||
unsigned int num_entries);
|
||||
unsigned int num_entries,
|
||||
bool use_scratch);
|
||||
void (*insert_entries)(struct i915_address_space *vm,
|
||||
struct sg_table *st,
|
||||
unsigned int first_entry,
|
||||
|
@ -2065,6 +2067,8 @@ void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
|
|||
void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
|
||||
struct drm_i915_gem_object *obj);
|
||||
|
||||
void i915_check_and_clear_faults(struct drm_device *dev);
|
||||
void i915_gem_suspend_gtt_mappings(struct drm_device *dev);
|
||||
void i915_gem_restore_gtt_mappings(struct drm_device *dev);
|
||||
int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
|
||||
void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
|
||||
|
|
|
@ -58,9 +58,10 @@
|
|||
#define HSW_WT_ELLC_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x6)
|
||||
|
||||
static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
|
||||
enum i915_cache_level level)
|
||||
enum i915_cache_level level,
|
||||
bool valid)
|
||||
{
|
||||
gen6_gtt_pte_t pte = GEN6_PTE_VALID;
|
||||
gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
|
||||
pte |= GEN6_PTE_ADDR_ENCODE(addr);
|
||||
|
||||
switch (level) {
|
||||
|
@ -79,9 +80,10 @@ static gen6_gtt_pte_t snb_pte_encode(dma_addr_t addr,
|
|||
}
|
||||
|
||||
static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
|
||||
enum i915_cache_level level)
|
||||
enum i915_cache_level level,
|
||||
bool valid)
|
||||
{
|
||||
gen6_gtt_pte_t pte = GEN6_PTE_VALID;
|
||||
gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
|
||||
pte |= GEN6_PTE_ADDR_ENCODE(addr);
|
||||
|
||||
switch (level) {
|
||||
|
@ -105,9 +107,10 @@ static gen6_gtt_pte_t ivb_pte_encode(dma_addr_t addr,
|
|||
#define BYT_PTE_SNOOPED_BY_CPU_CACHES (1 << 2)
|
||||
|
||||
static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
|
||||
enum i915_cache_level level)
|
||||
enum i915_cache_level level,
|
||||
bool valid)
|
||||
{
|
||||
gen6_gtt_pte_t pte = GEN6_PTE_VALID;
|
||||
gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
|
||||
pte |= GEN6_PTE_ADDR_ENCODE(addr);
|
||||
|
||||
/* Mark the page as writeable. Other platforms don't have a
|
||||
|
@ -122,9 +125,10 @@ static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
|
|||
}
|
||||
|
||||
static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
|
||||
enum i915_cache_level level)
|
||||
enum i915_cache_level level,
|
||||
bool valid)
|
||||
{
|
||||
gen6_gtt_pte_t pte = GEN6_PTE_VALID;
|
||||
gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
|
||||
pte |= HSW_PTE_ADDR_ENCODE(addr);
|
||||
|
||||
if (level != I915_CACHE_NONE)
|
||||
|
@ -134,9 +138,10 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr,
|
|||
}
|
||||
|
||||
static gen6_gtt_pte_t iris_pte_encode(dma_addr_t addr,
|
||||
enum i915_cache_level level)
|
||||
enum i915_cache_level level,
|
||||
bool valid)
|
||||
{
|
||||
gen6_gtt_pte_t pte = GEN6_PTE_VALID;
|
||||
gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
|
||||
pte |= HSW_PTE_ADDR_ENCODE(addr);
|
||||
|
||||
switch (level) {
|
||||
|
@ -236,7 +241,8 @@ static int gen6_ppgtt_enable(struct drm_device *dev)
|
|||
/* PPGTT support for Sandybdrige/Gen6 and later */
|
||||
static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
|
||||
unsigned first_entry,
|
||||
unsigned num_entries)
|
||||
unsigned num_entries,
|
||||
bool use_scratch)
|
||||
{
|
||||
struct i915_hw_ppgtt *ppgtt =
|
||||
container_of(vm, struct i915_hw_ppgtt, base);
|
||||
|
@ -245,7 +251,7 @@ static void gen6_ppgtt_clear_range(struct i915_address_space *vm,
|
|||
unsigned first_pte = first_entry % I915_PPGTT_PT_ENTRIES;
|
||||
unsigned last_pte, i;
|
||||
|
||||
scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
|
||||
scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, true);
|
||||
|
||||
while (num_entries) {
|
||||
last_pte = first_pte + num_entries;
|
||||
|
@ -282,7 +288,7 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm,
|
|||
dma_addr_t page_addr;
|
||||
|
||||
page_addr = sg_page_iter_dma_address(&sg_iter);
|
||||
pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level);
|
||||
pt_vaddr[act_pte] = vm->pte_encode(page_addr, cache_level, true);
|
||||
if (++act_pte == I915_PPGTT_PT_ENTRIES) {
|
||||
kunmap_atomic(pt_vaddr);
|
||||
act_pt++;
|
||||
|
@ -367,7 +373,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
|
|||
}
|
||||
|
||||
ppgtt->base.clear_range(&ppgtt->base, 0,
|
||||
ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES);
|
||||
ppgtt->num_pd_entries * I915_PPGTT_PT_ENTRIES, true);
|
||||
|
||||
ppgtt->pd_offset = first_pd_entry_in_global_pt * sizeof(gen6_gtt_pte_t);
|
||||
|
||||
|
@ -444,7 +450,8 @@ void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
|
|||
{
|
||||
ppgtt->base.clear_range(&ppgtt->base,
|
||||
i915_gem_obj_ggtt_offset(obj) >> PAGE_SHIFT,
|
||||
obj->base.size >> PAGE_SHIFT);
|
||||
obj->base.size >> PAGE_SHIFT,
|
||||
true);
|
||||
}
|
||||
|
||||
extern int intel_iommu_gfx_mapped;
|
||||
|
@ -485,15 +492,65 @@ static void undo_idling(struct drm_i915_private *dev_priv, bool interruptible)
|
|||
dev_priv->mm.interruptible = interruptible;
|
||||
}
|
||||
|
||||
void i915_check_and_clear_faults(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct intel_ring_buffer *ring;
|
||||
int i;
|
||||
|
||||
if (INTEL_INFO(dev)->gen < 6)
|
||||
return;
|
||||
|
||||
for_each_ring(ring, dev_priv, i) {
|
||||
u32 fault_reg;
|
||||
fault_reg = I915_READ(RING_FAULT_REG(ring));
|
||||
if (fault_reg & RING_FAULT_VALID) {
|
||||
DRM_DEBUG_DRIVER("Unexpected fault\n"
|
||||
"\tAddr: 0x%08lx\\n"
|
||||
"\tAddress space: %s\n"
|
||||
"\tSource ID: %d\n"
|
||||
"\tType: %d\n",
|
||||
fault_reg & PAGE_MASK,
|
||||
fault_reg & RING_FAULT_GTTSEL_MASK ? "GGTT" : "PPGTT",
|
||||
RING_FAULT_SRCID(fault_reg),
|
||||
RING_FAULT_FAULT_TYPE(fault_reg));
|
||||
I915_WRITE(RING_FAULT_REG(ring),
|
||||
fault_reg & ~RING_FAULT_VALID);
|
||||
}
|
||||
}
|
||||
POSTING_READ(RING_FAULT_REG(&dev_priv->ring[RCS]));
|
||||
}
|
||||
|
||||
void i915_gem_suspend_gtt_mappings(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
|
||||
/* Don't bother messing with faults pre GEN6 as we have little
|
||||
* documentation supporting that it's a good idea.
|
||||
*/
|
||||
if (INTEL_INFO(dev)->gen < 6)
|
||||
return;
|
||||
|
||||
i915_check_and_clear_faults(dev);
|
||||
|
||||
dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
|
||||
dev_priv->gtt.base.start / PAGE_SIZE,
|
||||
dev_priv->gtt.base.total / PAGE_SIZE,
|
||||
false);
|
||||
}
|
||||
|
||||
void i915_gem_restore_gtt_mappings(struct drm_device *dev)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = dev->dev_private;
|
||||
struct drm_i915_gem_object *obj;
|
||||
|
||||
i915_check_and_clear_faults(dev);
|
||||
|
||||
/* First fill our portion of the GTT with scratch pages */
|
||||
dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
|
||||
dev_priv->gtt.base.start / PAGE_SIZE,
|
||||
dev_priv->gtt.base.total / PAGE_SIZE);
|
||||
dev_priv->gtt.base.total / PAGE_SIZE,
|
||||
true);
|
||||
|
||||
list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
|
||||
i915_gem_clflush_object(obj, obj->pin_display);
|
||||
|
@ -536,7 +593,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
|
|||
|
||||
for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) {
|
||||
addr = sg_page_iter_dma_address(&sg_iter);
|
||||
iowrite32(vm->pte_encode(addr, level), >t_entries[i]);
|
||||
iowrite32(vm->pte_encode(addr, level, true), >t_entries[i]);
|
||||
i++;
|
||||
}
|
||||
|
||||
|
@ -548,7 +605,7 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
|
|||
*/
|
||||
if (i != 0)
|
||||
WARN_ON(readl(>t_entries[i-1]) !=
|
||||
vm->pte_encode(addr, level));
|
||||
vm->pte_encode(addr, level, true));
|
||||
|
||||
/* This next bit makes the above posting read even more important. We
|
||||
* want to flush the TLBs only after we're certain all the PTE updates
|
||||
|
@ -560,7 +617,8 @@ static void gen6_ggtt_insert_entries(struct i915_address_space *vm,
|
|||
|
||||
static void gen6_ggtt_clear_range(struct i915_address_space *vm,
|
||||
unsigned int first_entry,
|
||||
unsigned int num_entries)
|
||||
unsigned int num_entries,
|
||||
bool use_scratch)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = vm->dev->dev_private;
|
||||
gen6_gtt_pte_t scratch_pte, __iomem *gtt_base =
|
||||
|
@ -573,7 +631,8 @@ static void gen6_ggtt_clear_range(struct i915_address_space *vm,
|
|||
first_entry, num_entries, max_entries))
|
||||
num_entries = max_entries;
|
||||
|
||||
scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC);
|
||||
scratch_pte = vm->pte_encode(vm->scratch.addr, I915_CACHE_LLC, use_scratch);
|
||||
|
||||
for (i = 0; i < num_entries; i++)
|
||||
iowrite32(scratch_pte, >t_base[i]);
|
||||
readl(gtt_base);
|
||||
|
@ -594,7 +653,8 @@ static void i915_ggtt_insert_entries(struct i915_address_space *vm,
|
|||
|
||||
static void i915_ggtt_clear_range(struct i915_address_space *vm,
|
||||
unsigned int first_entry,
|
||||
unsigned int num_entries)
|
||||
unsigned int num_entries,
|
||||
bool unused)
|
||||
{
|
||||
intel_gtt_clear_range(first_entry, num_entries);
|
||||
}
|
||||
|
@ -622,7 +682,8 @@ void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj)
|
|||
|
||||
dev_priv->gtt.base.clear_range(&dev_priv->gtt.base,
|
||||
entry,
|
||||
obj->base.size >> PAGE_SHIFT);
|
||||
obj->base.size >> PAGE_SHIFT,
|
||||
true);
|
||||
|
||||
obj->has_global_gtt_mapping = 0;
|
||||
}
|
||||
|
@ -709,11 +770,11 @@ void i915_gem_setup_global_gtt(struct drm_device *dev,
|
|||
const unsigned long count = (hole_end - hole_start) / PAGE_SIZE;
|
||||
DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
|
||||
hole_start, hole_end);
|
||||
ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count);
|
||||
ggtt_vm->clear_range(ggtt_vm, hole_start / PAGE_SIZE, count, true);
|
||||
}
|
||||
|
||||
/* And finally clear the reserved guard page */
|
||||
ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1);
|
||||
ggtt_vm->clear_range(ggtt_vm, end / PAGE_SIZE - 1, 1, true);
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
|
@ -604,6 +604,10 @@
|
|||
#define ARB_MODE_SWIZZLE_IVB (1<<5)
|
||||
#define RENDER_HWS_PGA_GEN7 (0x04080)
|
||||
#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
|
||||
#define RING_FAULT_GTTSEL_MASK (1<<11)
|
||||
#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
|
||||
#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
|
||||
#define RING_FAULT_VALID (1<<0)
|
||||
#define DONE_REG 0x40b0
|
||||
#define BSD_HWS_PGA_GEN7 (0x04180)
|
||||
#define BLT_HWS_PGA_GEN7 (0x04280)
|
||||
|
@ -4279,7 +4283,9 @@
|
|||
#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
|
||||
|
||||
#define SOUTH_DSPCLK_GATE_D 0xc2020
|
||||
#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
|
||||
#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
|
||||
#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
|
||||
#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
|
||||
|
||||
/* CPU: FDI_TX */
|
||||
|
|
|
@ -4759,7 +4759,9 @@ static void cpt_init_clock_gating(struct drm_device *dev)
|
|||
* gating for the panel power sequencer or it will fail to
|
||||
* start up when no ports are active.
|
||||
*/
|
||||
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
|
||||
I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
|
||||
PCH_DPLUNIT_CLOCK_GATE_DISABLE |
|
||||
PCH_CPUNIT_CLOCK_GATE_DISABLE);
|
||||
I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
|
||||
DPLS_EDP_PPS_FIX_DIS);
|
||||
/* The below fixes the weird display corruption, a few pixels shifted
|
||||
|
|
|
@ -707,24 +707,37 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
|||
switch (connector->connector_type) {
|
||||
case DRM_MODE_CONNECTOR_DVII:
|
||||
case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
|
||||
if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
|
||||
(drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_AUTO)))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else if (radeon_connector->use_digital)
|
||||
if (radeon_audio != 0) {
|
||||
if (radeon_connector->use_digital &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_ENABLE))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_AUTO))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else if (radeon_connector->use_digital)
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
else
|
||||
return ATOM_ENCODER_MODE_CRT;
|
||||
} else if (radeon_connector->use_digital) {
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
else
|
||||
} else {
|
||||
return ATOM_ENCODER_MODE_CRT;
|
||||
}
|
||||
break;
|
||||
case DRM_MODE_CONNECTOR_DVID:
|
||||
case DRM_MODE_CONNECTOR_HDMIA:
|
||||
default:
|
||||
if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
|
||||
(drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_AUTO)))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else
|
||||
if (radeon_audio != 0) {
|
||||
if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_AUTO))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
} else {
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
}
|
||||
break;
|
||||
case DRM_MODE_CONNECTOR_LVDS:
|
||||
return ATOM_ENCODER_MODE_LVDS;
|
||||
|
@ -732,14 +745,19 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
|
|||
case DRM_MODE_CONNECTOR_DisplayPort:
|
||||
dig_connector = radeon_connector->con_priv;
|
||||
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
|
||||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
|
||||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
|
||||
return ATOM_ENCODER_MODE_DP;
|
||||
else if ((radeon_connector->audio == RADEON_AUDIO_ENABLE) ||
|
||||
(drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_AUTO)))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else
|
||||
} else if (radeon_audio != 0) {
|
||||
if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
|
||||
(radeon_connector->audio == RADEON_AUDIO_AUTO))
|
||||
return ATOM_ENCODER_MODE_HDMI;
|
||||
else
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
} else {
|
||||
return ATOM_ENCODER_MODE_DVI;
|
||||
}
|
||||
break;
|
||||
case DRM_MODE_CONNECTOR_eDP:
|
||||
return ATOM_ENCODER_MODE_DP;
|
||||
|
@ -1655,7 +1673,7 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
|
|||
* does the same thing and more.
|
||||
*/
|
||||
if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730) &&
|
||||
(rdev->family != CHIP_RS880))
|
||||
(rdev->family != CHIP_RS780) && (rdev->family != CHIP_RS880))
|
||||
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
|
||||
}
|
||||
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
|
||||
|
|
|
@ -1694,6 +1694,7 @@ static int cik_init_microcode(struct radeon_device *rdev)
|
|||
fw_name);
|
||||
release_firmware(rdev->smc_fw);
|
||||
rdev->smc_fw = NULL;
|
||||
err = 0;
|
||||
} else if (rdev->smc_fw->size != smc_req_size) {
|
||||
printk(KERN_ERR
|
||||
"cik_smc: Bogus length %zu in firmware \"%s\"\n",
|
||||
|
@ -3182,6 +3183,7 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: failed to get ib (%d).\n", r);
|
||||
radeon_scratch_free(rdev, scratch);
|
||||
return r;
|
||||
}
|
||||
ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
|
||||
|
@ -3198,6 +3200,8 @@ int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
|
|||
r = radeon_fence_wait(ib.fence, false);
|
||||
if (r) {
|
||||
DRM_ERROR("radeon: fence wait failed (%d).\n", r);
|
||||
radeon_scratch_free(rdev, scratch);
|
||||
radeon_ib_free(rdev, &ib);
|
||||
return r;
|
||||
}
|
||||
for (i = 0; i < rdev->usec_timeout; i++) {
|
||||
|
|
|
@ -113,6 +113,9 @@ void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
|
|||
u8 *sadb;
|
||||
int sad_count;
|
||||
|
||||
/* XXX: setting this register causes hangs on some asics */
|
||||
return;
|
||||
|
||||
if (!dig->afmt->pin)
|
||||
return;
|
||||
|
||||
|
|
|
@ -67,6 +67,9 @@ static void dce4_afmt_write_speaker_allocation(struct drm_encoder *encoder)
|
|||
u8 *sadb;
|
||||
int sad_count;
|
||||
|
||||
/* XXX: setting this register causes hangs on some asics */
|
||||
return;
|
||||
|
||||
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
|
||||
if (connector->encoder == encoder)
|
||||
radeon_connector = to_radeon_connector(connector);
|
||||
|
|
|
@ -804,6 +804,7 @@ int ni_init_microcode(struct radeon_device *rdev)
|
|||
fw_name);
|
||||
release_firmware(rdev->smc_fw);
|
||||
rdev->smc_fw = NULL;
|
||||
err = 0;
|
||||
} else if (rdev->smc_fw->size != smc_req_size) {
|
||||
printk(KERN_ERR
|
||||
"ni_mc: Bogus length %zu in firmware \"%s\"\n",
|
||||
|
|
|
@ -2302,6 +2302,7 @@ int r600_init_microcode(struct radeon_device *rdev)
|
|||
fw_name);
|
||||
release_firmware(rdev->smc_fw);
|
||||
rdev->smc_fw = NULL;
|
||||
err = 0;
|
||||
} else if (rdev->smc_fw->size != smc_req_size) {
|
||||
printk(KERN_ERR
|
||||
"smc: Bogus length %zu in firmware \"%s\"\n",
|
||||
|
|
|
@ -309,6 +309,9 @@ static void dce3_2_afmt_write_speaker_allocation(struct drm_encoder *encoder)
|
|||
u8 *sadb;
|
||||
int sad_count;
|
||||
|
||||
/* XXX: setting this register causes hangs on some asics */
|
||||
return;
|
||||
|
||||
list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
|
||||
if (connector->encoder == encoder)
|
||||
radeon_connector = to_radeon_connector(connector);
|
||||
|
|
|
@ -1658,9 +1658,12 @@ radeon_add_atom_connector(struct drm_device *dev,
|
|||
drm_object_attach_property(&radeon_connector->base.base,
|
||||
rdev->mode_info.underscan_vborder_property,
|
||||
0);
|
||||
drm_object_attach_property(&radeon_connector->base.base,
|
||||
rdev->mode_info.audio_property,
|
||||
RADEON_AUDIO_DISABLE);
|
||||
if (radeon_audio != 0)
|
||||
drm_object_attach_property(&radeon_connector->base.base,
|
||||
rdev->mode_info.audio_property,
|
||||
(radeon_audio == 1) ?
|
||||
RADEON_AUDIO_AUTO :
|
||||
RADEON_AUDIO_DISABLE);
|
||||
subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = true;
|
||||
if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
|
||||
|
@ -1754,10 +1757,12 @@ radeon_add_atom_connector(struct drm_device *dev,
|
|||
rdev->mode_info.underscan_vborder_property,
|
||||
0);
|
||||
}
|
||||
if (ASIC_IS_DCE2(rdev)) {
|
||||
if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
|
||||
drm_object_attach_property(&radeon_connector->base.base,
|
||||
rdev->mode_info.audio_property,
|
||||
RADEON_AUDIO_DISABLE);
|
||||
rdev->mode_info.audio_property,
|
||||
(radeon_audio == 1) ?
|
||||
RADEON_AUDIO_AUTO :
|
||||
RADEON_AUDIO_DISABLE);
|
||||
}
|
||||
if (connector_type == DRM_MODE_CONNECTOR_DVII) {
|
||||
radeon_connector->dac_load_detect = true;
|
||||
|
@ -1799,10 +1804,12 @@ radeon_add_atom_connector(struct drm_device *dev,
|
|||
rdev->mode_info.underscan_vborder_property,
|
||||
0);
|
||||
}
|
||||
if (ASIC_IS_DCE2(rdev)) {
|
||||
if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
|
||||
drm_object_attach_property(&radeon_connector->base.base,
|
||||
rdev->mode_info.audio_property,
|
||||
RADEON_AUDIO_DISABLE);
|
||||
rdev->mode_info.audio_property,
|
||||
(radeon_audio == 1) ?
|
||||
RADEON_AUDIO_AUTO :
|
||||
RADEON_AUDIO_DISABLE);
|
||||
}
|
||||
subpixel_order = SubPixelHorizontalRGB;
|
||||
connector->interlace_allowed = true;
|
||||
|
@ -1843,10 +1850,12 @@ radeon_add_atom_connector(struct drm_device *dev,
|
|||
rdev->mode_info.underscan_vborder_property,
|
||||
0);
|
||||
}
|
||||
if (ASIC_IS_DCE2(rdev)) {
|
||||
if (ASIC_IS_DCE2(rdev) && (radeon_audio != 0)) {
|
||||
drm_object_attach_property(&radeon_connector->base.base,
|
||||
rdev->mode_info.audio_property,
|
||||
RADEON_AUDIO_DISABLE);
|
||||
rdev->mode_info.audio_property,
|
||||
(radeon_audio == 1) ?
|
||||
RADEON_AUDIO_AUTO :
|
||||
RADEON_AUDIO_DISABLE);
|
||||
}
|
||||
connector->interlace_allowed = true;
|
||||
/* in theory with a DP to VGA converter... */
|
||||
|
|
|
@ -85,9 +85,8 @@ static int radeon_cs_parser_relocs(struct radeon_cs_parser *p)
|
|||
VRAM, also but everything into VRAM on AGP cards to avoid
|
||||
image corruptions */
|
||||
if (p->ring == R600_RING_TYPE_UVD_INDEX &&
|
||||
p->rdev->family < CHIP_PALM &&
|
||||
(i == 0 || drm_pci_device_is_agp(p->rdev->ddev))) {
|
||||
|
||||
/* TODO: is this still needed for NI+ ? */
|
||||
p->relocs[i].lobj.domain =
|
||||
RADEON_GEM_DOMAIN_VRAM;
|
||||
|
||||
|
|
|
@ -153,7 +153,7 @@ int radeon_benchmarking = 0;
|
|||
int radeon_testing = 0;
|
||||
int radeon_connector_table = 0;
|
||||
int radeon_tv = 1;
|
||||
int radeon_audio = 1;
|
||||
int radeon_audio = -1;
|
||||
int radeon_disp_priority = 0;
|
||||
int radeon_hw_i2c = 0;
|
||||
int radeon_pcie_gen2 = -1;
|
||||
|
@ -196,7 +196,7 @@ module_param_named(connector_table, radeon_connector_table, int, 0444);
|
|||
MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
|
||||
module_param_named(tv, radeon_tv, int, 0444);
|
||||
|
||||
MODULE_PARM_DESC(audio, "Audio enable (1 = enable)");
|
||||
MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
|
||||
module_param_named(audio, radeon_audio, int, 0444);
|
||||
|
||||
MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
|
||||
|
|
|
@ -476,7 +476,8 @@ static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (p->rdev->family < CHIP_PALM && (cmd == 0 || cmd == 0x3) &&
|
||||
/* TODO: is this still necessary on NI+ ? */
|
||||
if ((cmd == 0 || cmd == 0x3) &&
|
||||
(start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) {
|
||||
DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n",
|
||||
start, end);
|
||||
|
|
|
@ -1681,6 +1681,7 @@ static int si_init_microcode(struct radeon_device *rdev)
|
|||
fw_name);
|
||||
release_firmware(rdev->smc_fw);
|
||||
rdev->smc_fw = NULL;
|
||||
err = 0;
|
||||
} else if (rdev->smc_fw->size != smc_req_size) {
|
||||
printk(KERN_ERR
|
||||
"si_smc: Bogus length %zu in firmware \"%s\"\n",
|
||||
|
|
|
@ -212,8 +212,8 @@ int uvd_v1_0_start(struct radeon_device *rdev)
|
|||
/* enable VCPU clock */
|
||||
WREG32(UVD_VCPU_CNTL, 1 << 9);
|
||||
|
||||
/* enable UMC and NC0 */
|
||||
WREG32_P(UVD_LMI_CTRL2, 1 << 13, ~((1 << 8) | (1 << 13)));
|
||||
/* enable UMC */
|
||||
WREG32_P(UVD_LMI_CTRL2, 0, ~(1 << 8));
|
||||
|
||||
/* boot up the VCPU */
|
||||
WREG32(UVD_SOFT_RESET, 0);
|
||||
|
|
|
@ -740,9 +740,17 @@ static void vmw_postclose(struct drm_device *dev,
|
|||
struct vmw_fpriv *vmw_fp;
|
||||
|
||||
vmw_fp = vmw_fpriv(file_priv);
|
||||
ttm_object_file_release(&vmw_fp->tfile);
|
||||
if (vmw_fp->locked_master)
|
||||
|
||||
if (vmw_fp->locked_master) {
|
||||
struct vmw_master *vmaster =
|
||||
vmw_master(vmw_fp->locked_master);
|
||||
|
||||
ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
|
||||
ttm_vt_unlock(&vmaster->lock);
|
||||
drm_master_put(&vmw_fp->locked_master);
|
||||
}
|
||||
|
||||
ttm_object_file_release(&vmw_fp->tfile);
|
||||
kfree(vmw_fp);
|
||||
}
|
||||
|
||||
|
@ -925,14 +933,13 @@ static void vmw_master_drop(struct drm_device *dev,
|
|||
|
||||
vmw_fp->locked_master = drm_master_get(file_priv->master);
|
||||
ret = ttm_vt_lock(&vmaster->lock, false, vmw_fp->tfile);
|
||||
vmw_execbuf_release_pinned_bo(dev_priv);
|
||||
|
||||
if (unlikely((ret != 0))) {
|
||||
DRM_ERROR("Unable to lock TTM at VT switch.\n");
|
||||
drm_master_put(&vmw_fp->locked_master);
|
||||
}
|
||||
|
||||
ttm_lock_set_kill(&vmaster->lock, true, SIGTERM);
|
||||
ttm_lock_set_kill(&vmaster->lock, false, SIGTERM);
|
||||
vmw_execbuf_release_pinned_bo(dev_priv);
|
||||
|
||||
if (!dev_priv->enable_fb) {
|
||||
ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM);
|
||||
|
|
|
@ -970,7 +970,7 @@ void vmw_resource_unreserve(struct vmw_resource *res,
|
|||
if (new_backup)
|
||||
res->backup_offset = new_backup_offset;
|
||||
|
||||
if (!res->func->may_evict)
|
||||
if (!res->func->may_evict || res->id == -1)
|
||||
return;
|
||||
|
||||
write_lock(&dev_priv->resource_lock);
|
||||
|
|
|
@ -319,7 +319,7 @@ static s32 item_sdata(struct hid_item *item)
|
|||
|
||||
static int hid_parser_global(struct hid_parser *parser, struct hid_item *item)
|
||||
{
|
||||
__u32 raw_value;
|
||||
__s32 raw_value;
|
||||
switch (item->tag) {
|
||||
case HID_GLOBAL_ITEM_TAG_PUSH:
|
||||
|
||||
|
@ -370,10 +370,11 @@ static int hid_parser_global(struct hid_parser *parser, struct hid_item *item)
|
|||
return 0;
|
||||
|
||||
case HID_GLOBAL_ITEM_TAG_UNIT_EXPONENT:
|
||||
/* Units exponent negative numbers are given through a
|
||||
* two's complement.
|
||||
* See "6.2.2.7 Global Items" for more information. */
|
||||
raw_value = item_udata(item);
|
||||
/* Many devices provide unit exponent as a two's complement
|
||||
* nibble due to the common misunderstanding of HID
|
||||
* specification 1.11, 6.2.2.7 Global Items. Attempt to handle
|
||||
* both this and the standard encoding. */
|
||||
raw_value = item_sdata(item);
|
||||
if (!(raw_value & 0xfffffff0))
|
||||
parser->global.unit_exponent = hid_snto32(raw_value, 4);
|
||||
else
|
||||
|
@ -1870,6 +1871,7 @@ static const struct hid_device_id hid_have_special_driver[] = {
|
|||
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_BT) },
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE) },
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO2, USB_DEVICE_ID_NINTENDO_WIIMOTE) },
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO, USB_DEVICE_ID_NINTENDO_WIIMOTE2) },
|
||||
{ }
|
||||
};
|
||||
|
|
|
@ -633,6 +633,7 @@
|
|||
#define USB_DEVICE_ID_NEXTWINDOW_TOUCHSCREEN 0x0003
|
||||
|
||||
#define USB_VENDOR_ID_NINTENDO 0x057e
|
||||
#define USB_VENDOR_ID_NINTENDO2 0x054c
|
||||
#define USB_DEVICE_ID_NINTENDO_WIIMOTE 0x0306
|
||||
#define USB_DEVICE_ID_NINTENDO_WIIMOTE2 0x0330
|
||||
|
||||
|
@ -792,6 +793,8 @@
|
|||
#define USB_DEVICE_ID_SYNAPTICS_COMP_TP 0x0009
|
||||
#define USB_DEVICE_ID_SYNAPTICS_WTP 0x0010
|
||||
#define USB_DEVICE_ID_SYNAPTICS_DPAD 0x0013
|
||||
#define USB_DEVICE_ID_SYNAPTICS_LTS1 0x0af8
|
||||
#define USB_DEVICE_ID_SYNAPTICS_LTS2 0x1d10
|
||||
|
||||
#define USB_VENDOR_ID_THINGM 0x27b8
|
||||
#define USB_DEVICE_ID_BLINK1 0x01ed
|
||||
|
@ -919,4 +922,7 @@
|
|||
#define USB_VENDOR_ID_PRIMAX 0x0461
|
||||
#define USB_DEVICE_ID_PRIMAX_KEYBOARD 0x4e05
|
||||
|
||||
#define USB_VENDOR_ID_SIS 0x0457
|
||||
#define USB_DEVICE_ID_SIS_TS 0x1013
|
||||
|
||||
#endif
|
||||
|
|
|
@ -192,6 +192,7 @@ static int hidinput_setkeycode(struct input_dev *dev,
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* hidinput_calc_abs_res - calculate an absolute axis resolution
|
||||
* @field: the HID report field to calculate resolution for
|
||||
|
@ -234,23 +235,17 @@ __s32 hidinput_calc_abs_res(const struct hid_field *field, __u16 code)
|
|||
case ABS_MT_TOOL_Y:
|
||||
case ABS_MT_TOUCH_MAJOR:
|
||||
case ABS_MT_TOUCH_MINOR:
|
||||
if (field->unit & 0xffffff00) /* Not a length */
|
||||
return 0;
|
||||
unit_exponent += hid_snto32(field->unit >> 4, 4) - 1;
|
||||
switch (field->unit & 0xf) {
|
||||
case 0x1: /* If centimeters */
|
||||
if (field->unit == 0x11) { /* If centimeters */
|
||||
/* Convert to millimeters */
|
||||
unit_exponent += 1;
|
||||
break;
|
||||
case 0x3: /* If inches */
|
||||
} else if (field->unit == 0x13) { /* If inches */
|
||||
/* Convert to millimeters */
|
||||
prev = physical_extents;
|
||||
physical_extents *= 254;
|
||||
if (physical_extents < prev)
|
||||
return 0;
|
||||
unit_exponent -= 1;
|
||||
break;
|
||||
default:
|
||||
} else {
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
|
|
@ -834,7 +834,8 @@ static void wiimote_init_set_type(struct wiimote_data *wdata,
|
|||
goto done;
|
||||
}
|
||||
|
||||
if (vendor == USB_VENDOR_ID_NINTENDO) {
|
||||
if (vendor == USB_VENDOR_ID_NINTENDO ||
|
||||
vendor == USB_VENDOR_ID_NINTENDO2) {
|
||||
if (product == USB_DEVICE_ID_NINTENDO_WIIMOTE) {
|
||||
devtype = WIIMOTE_DEV_GEN10;
|
||||
goto done;
|
||||
|
@ -1855,6 +1856,8 @@ static void wiimote_hid_remove(struct hid_device *hdev)
|
|||
static const struct hid_device_id wiimote_hid_devices[] = {
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
|
||||
USB_DEVICE_ID_NINTENDO_WIIMOTE) },
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO2,
|
||||
USB_DEVICE_ID_NINTENDO_WIIMOTE) },
|
||||
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_NINTENDO,
|
||||
USB_DEVICE_ID_NINTENDO_WIIMOTE2) },
|
||||
{ }
|
||||
|
|
|
@ -110,6 +110,9 @@ static const struct hid_blacklist {
|
|||
{ USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_MOUSEPEN_I608X, HID_QUIRK_MULTI_INPUT },
|
||||
{ USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_EASYPEN_M610X, HID_QUIRK_MULTI_INPUT },
|
||||
{ USB_VENDOR_ID_NTRIG, USB_DEVICE_ID_NTRIG_DUOSENSE, HID_QUIRK_NO_INIT_REPORTS },
|
||||
{ USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_LTS1, HID_QUIRK_NO_INIT_REPORTS },
|
||||
{ USB_VENDOR_ID_SYNAPTICS, USB_DEVICE_ID_SYNAPTICS_LTS2, HID_QUIRK_NO_INIT_REPORTS },
|
||||
{ USB_VENDOR_ID_SIS, USB_DEVICE_ID_SIS_TS, HID_QUIRK_NO_INIT_REPORTS },
|
||||
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
|
|
@ -31,6 +31,17 @@ config INFINIBAND_USER_ACCESS
|
|||
libibverbs, libibcm and a hardware driver library from
|
||||
<http://www.openfabrics.org/git/>.
|
||||
|
||||
config INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
bool "Experimental and unstable ABI for userspace access to flow steering verbs"
|
||||
depends on INFINIBAND_USER_ACCESS
|
||||
depends on STAGING
|
||||
---help---
|
||||
The final ABI for userspace access to flow steering verbs
|
||||
has not been defined. To use the current ABI, *WHICH WILL
|
||||
CHANGE IN THE FUTURE*, say Y here.
|
||||
|
||||
If unsure, say N.
|
||||
|
||||
config INFINIBAND_USER_MEM
|
||||
bool
|
||||
depends on INFINIBAND_USER_ACCESS != n
|
||||
|
|
|
@ -217,7 +217,9 @@ IB_UVERBS_DECLARE_CMD(destroy_srq);
|
|||
IB_UVERBS_DECLARE_CMD(create_xsrq);
|
||||
IB_UVERBS_DECLARE_CMD(open_xrcd);
|
||||
IB_UVERBS_DECLARE_CMD(close_xrcd);
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
IB_UVERBS_DECLARE_CMD(create_flow);
|
||||
IB_UVERBS_DECLARE_CMD(destroy_flow);
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
|
||||
#endif /* UVERBS_H */
|
||||
|
|
|
@ -54,7 +54,9 @@ static struct uverbs_lock_class qp_lock_class = { .name = "QP-uobj" };
|
|||
static struct uverbs_lock_class ah_lock_class = { .name = "AH-uobj" };
|
||||
static struct uverbs_lock_class srq_lock_class = { .name = "SRQ-uobj" };
|
||||
static struct uverbs_lock_class xrcd_lock_class = { .name = "XRCD-uobj" };
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
static struct uverbs_lock_class rule_lock_class = { .name = "RULE-uobj" };
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
|
||||
#define INIT_UDATA(udata, ibuf, obuf, ilen, olen) \
|
||||
do { \
|
||||
|
@ -2599,6 +2601,7 @@ out_put:
|
|||
return ret ? ret : in_len;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
static int kern_spec_to_ib_spec(struct ib_kern_spec *kern_spec,
|
||||
union ib_flow_spec *ib_spec)
|
||||
{
|
||||
|
@ -2824,6 +2827,7 @@ ssize_t ib_uverbs_destroy_flow(struct ib_uverbs_file *file,
|
|||
|
||||
return ret ? ret : in_len;
|
||||
}
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
|
||||
static int __uverbs_create_xsrq(struct ib_uverbs_file *file,
|
||||
struct ib_uverbs_create_xsrq *cmd,
|
||||
|
|
|
@ -115,8 +115,10 @@ static ssize_t (*uverbs_cmd_table[])(struct ib_uverbs_file *file,
|
|||
[IB_USER_VERBS_CMD_CLOSE_XRCD] = ib_uverbs_close_xrcd,
|
||||
[IB_USER_VERBS_CMD_CREATE_XSRQ] = ib_uverbs_create_xsrq,
|
||||
[IB_USER_VERBS_CMD_OPEN_QP] = ib_uverbs_open_qp,
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
[IB_USER_VERBS_CMD_CREATE_FLOW] = ib_uverbs_create_flow,
|
||||
[IB_USER_VERBS_CMD_DESTROY_FLOW] = ib_uverbs_destroy_flow
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
};
|
||||
|
||||
static void ib_uverbs_add_one(struct ib_device *device);
|
||||
|
@ -605,6 +607,7 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
|
|||
if (!(file->device->ib_dev->uverbs_cmd_mask & (1ull << hdr.command)))
|
||||
return -ENOSYS;
|
||||
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
if (hdr.command >= IB_USER_VERBS_CMD_THRESHOLD) {
|
||||
struct ib_uverbs_cmd_hdr_ex hdr_ex;
|
||||
|
||||
|
@ -621,6 +624,7 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
|
|||
(hdr_ex.out_words +
|
||||
hdr_ex.provider_out_words) * 4);
|
||||
} else {
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
if (hdr.in_words * 4 != count)
|
||||
return -EINVAL;
|
||||
|
||||
|
@ -628,7 +632,9 @@ static ssize_t ib_uverbs_write(struct file *filp, const char __user *buf,
|
|||
buf + sizeof(hdr),
|
||||
hdr.in_words * 4,
|
||||
hdr.out_words * 4);
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
}
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
}
|
||||
|
||||
static int ib_uverbs_mmap(struct file *filp, struct vm_area_struct *vma)
|
||||
|
|
|
@ -1691,9 +1691,11 @@ static void *mlx4_ib_add(struct mlx4_dev *dev)
|
|||
ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
|
||||
ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
|
||||
|
||||
#ifdef CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING
|
||||
ibdev->ib_dev.uverbs_cmd_mask |=
|
||||
(1ull << IB_USER_VERBS_CMD_CREATE_FLOW) |
|
||||
(1ull << IB_USER_VERBS_CMD_DESTROY_FLOW);
|
||||
#endif /* CONFIG_INFINIBAND_EXPERIMENTAL_UVERBS_FLOW_STEERING */
|
||||
}
|
||||
|
||||
mlx4_ib_alloc_eqs(dev, ibdev);
|
||||
|
|
|
@ -594,7 +594,7 @@ isert_connect_release(struct isert_conn *isert_conn)
|
|||
|
||||
pr_debug("Entering isert_connect_release(): >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n");
|
||||
|
||||
if (device->use_frwr)
|
||||
if (device && device->use_frwr)
|
||||
isert_conn_free_frwr_pool(isert_conn);
|
||||
|
||||
if (isert_conn->conn_qp) {
|
||||
|
|
|
@ -1000,7 +1000,7 @@ static void request_write(struct cached_dev *dc, struct search *s)
|
|||
|
||||
if (bio->bi_rw & REQ_FLUSH) {
|
||||
/* Also need to send a flush to the backing device */
|
||||
struct bio *flush = bio_alloc_bioset(0, GFP_NOIO,
|
||||
struct bio *flush = bio_alloc_bioset(GFP_NOIO, 0,
|
||||
dc->disk.bio_split);
|
||||
|
||||
flush->bi_rw = WRITE_FLUSH;
|
||||
|
|
|
@ -8111,6 +8111,7 @@ static int md_set_badblocks(struct badblocks *bb, sector_t s, int sectors,
|
|||
u64 *p;
|
||||
int lo, hi;
|
||||
int rv = 1;
|
||||
unsigned long flags;
|
||||
|
||||
if (bb->shift < 0)
|
||||
/* badblocks are disabled */
|
||||
|
@ -8125,7 +8126,7 @@ static int md_set_badblocks(struct badblocks *bb, sector_t s, int sectors,
|
|||
sectors = next - s;
|
||||
}
|
||||
|
||||
write_seqlock_irq(&bb->lock);
|
||||
write_seqlock_irqsave(&bb->lock, flags);
|
||||
|
||||
p = bb->page;
|
||||
lo = 0;
|
||||
|
@ -8241,7 +8242,7 @@ static int md_set_badblocks(struct badblocks *bb, sector_t s, int sectors,
|
|||
bb->changed = 1;
|
||||
if (!acknowledged)
|
||||
bb->unacked_exist = 1;
|
||||
write_sequnlock_irq(&bb->lock);
|
||||
write_sequnlock_irqrestore(&bb->lock, flags);
|
||||
|
||||
return rv;
|
||||
}
|
||||
|
|
|
@ -1479,6 +1479,7 @@ static int raid1_spare_active(struct mddev *mddev)
|
|||
}
|
||||
}
|
||||
if (rdev
|
||||
&& rdev->recovery_offset == MaxSector
|
||||
&& !test_bit(Faulty, &rdev->flags)
|
||||
&& !test_and_set_bit(In_sync, &rdev->flags)) {
|
||||
count++;
|
||||
|
|
|
@ -1782,6 +1782,7 @@ static int raid10_spare_active(struct mddev *mddev)
|
|||
}
|
||||
sysfs_notify_dirent_safe(tmp->replacement->sysfs_state);
|
||||
} else if (tmp->rdev
|
||||
&& tmp->rdev->recovery_offset == MaxSector
|
||||
&& !test_bit(Faulty, &tmp->rdev->flags)
|
||||
&& !test_and_set_bit(In_sync, &tmp->rdev->flags)) {
|
||||
count++;
|
||||
|
|
|
@ -778,6 +778,12 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
|
|||
bi->bi_io_vec[0].bv_len = STRIPE_SIZE;
|
||||
bi->bi_io_vec[0].bv_offset = 0;
|
||||
bi->bi_size = STRIPE_SIZE;
|
||||
/*
|
||||
* If this is discard request, set bi_vcnt 0. We don't
|
||||
* want to confuse SCSI because SCSI will replace payload
|
||||
*/
|
||||
if (rw & REQ_DISCARD)
|
||||
bi->bi_vcnt = 0;
|
||||
if (rrdev)
|
||||
set_bit(R5_DOUBLE_LOCKED, &sh->dev[i].flags);
|
||||
|
||||
|
@ -816,6 +822,12 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
|
|||
rbi->bi_io_vec[0].bv_len = STRIPE_SIZE;
|
||||
rbi->bi_io_vec[0].bv_offset = 0;
|
||||
rbi->bi_size = STRIPE_SIZE;
|
||||
/*
|
||||
* If this is discard request, set bi_vcnt 0. We don't
|
||||
* want to confuse SCSI because SCSI will replace payload
|
||||
*/
|
||||
if (rw & REQ_DISCARD)
|
||||
rbi->bi_vcnt = 0;
|
||||
if (conf->mddev->gendisk)
|
||||
trace_block_bio_remap(bdev_get_queue(rbi->bi_bdev),
|
||||
rbi, disk_devt(conf->mddev->gendisk),
|
||||
|
@ -2910,6 +2922,14 @@ static void handle_stripe_clean_event(struct r5conf *conf,
|
|||
}
|
||||
/* now that discard is done we can proceed with any sync */
|
||||
clear_bit(STRIPE_DISCARD, &sh->state);
|
||||
/*
|
||||
* SCSI discard will change some bio fields and the stripe has
|
||||
* no updated data, so remove it from hash list and the stripe
|
||||
* will be reinitialized
|
||||
*/
|
||||
spin_lock_irq(&conf->device_lock);
|
||||
remove_hash(sh);
|
||||
spin_unlock_irq(&conf->device_lock);
|
||||
if (test_bit(STRIPE_SYNC_REQUESTED, &sh->state))
|
||||
set_bit(STRIPE_HANDLE, &sh->state);
|
||||
|
||||
|
|
|
@ -912,14 +912,8 @@ static int tda10071_init(struct dvb_frontend *fe)
|
|||
{ 0xd5, 0x03, 0x03 },
|
||||
};
|
||||
|
||||
/* firmware status */
|
||||
ret = tda10071_rd_reg(priv, 0x51, &tmp);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
if (!tmp) {
|
||||
if (priv->warm) {
|
||||
/* warm state - wake up device from sleep */
|
||||
priv->warm = 1;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(tab); i++) {
|
||||
ret = tda10071_wr_reg_mask(priv, tab[i].reg,
|
||||
|
@ -937,7 +931,6 @@ static int tda10071_init(struct dvb_frontend *fe)
|
|||
goto error;
|
||||
} else {
|
||||
/* cold state - try to download firmware */
|
||||
priv->warm = 0;
|
||||
|
||||
/* request the firmware, this will block and timeout */
|
||||
ret = request_firmware(&fw, fw_file, priv->i2c->dev.parent);
|
||||
|
|
|
@ -628,16 +628,13 @@ static int ad9389b_s_stream(struct v4l2_subdev *sd, int enable)
|
|||
|
||||
static const struct v4l2_dv_timings_cap ad9389b_timings_cap = {
|
||||
.type = V4L2_DV_BT_656_1120,
|
||||
.bt = {
|
||||
.max_width = 1920,
|
||||
.max_height = 1200,
|
||||
.min_pixelclock = 25000000,
|
||||
.max_pixelclock = 170000000,
|
||||
.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
/* keep this initialization for compatibility with GCC < 4.4.6 */
|
||||
.reserved = { 0 },
|
||||
V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
|
||||
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
|
||||
.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
|
||||
V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
|
||||
},
|
||||
V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
|
||||
V4L2_DV_BT_CAP_CUSTOM)
|
||||
};
|
||||
|
||||
static int ad9389b_s_dv_timings(struct v4l2_subdev *sd,
|
||||
|
|
|
@ -119,16 +119,14 @@ static int adv7511_s_clock_freq(struct v4l2_subdev *sd, u32 freq);
|
|||
|
||||
static const struct v4l2_dv_timings_cap adv7511_timings_cap = {
|
||||
.type = V4L2_DV_BT_656_1120,
|
||||
.bt = {
|
||||
.max_width = ADV7511_MAX_WIDTH,
|
||||
.max_height = ADV7511_MAX_HEIGHT,
|
||||
.min_pixelclock = ADV7511_MIN_PIXELCLOCK,
|
||||
.max_pixelclock = ADV7511_MAX_PIXELCLOCK,
|
||||
.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
/* keep this initialization for compatibility with GCC < 4.4.6 */
|
||||
.reserved = { 0 },
|
||||
V4L2_INIT_BT_TIMINGS(0, ADV7511_MAX_WIDTH, 0, ADV7511_MAX_HEIGHT,
|
||||
ADV7511_MIN_PIXELCLOCK, ADV7511_MAX_PIXELCLOCK,
|
||||
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
|
||||
.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
|
||||
V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
|
||||
},
|
||||
V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
|
||||
V4L2_DV_BT_CAP_CUSTOM)
|
||||
};
|
||||
|
||||
static inline struct adv7511_state *get_adv7511_state(struct v4l2_subdev *sd)
|
||||
|
@ -1126,6 +1124,7 @@ static int adv7511_probe(struct i2c_client *client, const struct i2c_device_id *
|
|||
state->i2c_edid = i2c_new_dummy(client->adapter, state->i2c_edid_addr >> 1);
|
||||
if (state->i2c_edid == NULL) {
|
||||
v4l2_err(sd, "failed to register edid i2c client\n");
|
||||
err = -ENOMEM;
|
||||
goto err_entity;
|
||||
}
|
||||
|
||||
|
@ -1133,6 +1132,7 @@ static int adv7511_probe(struct i2c_client *client, const struct i2c_device_id *
|
|||
state->work_queue = create_singlethread_workqueue(sd->name);
|
||||
if (state->work_queue == NULL) {
|
||||
v4l2_err(sd, "could not create workqueue\n");
|
||||
err = -ENOMEM;
|
||||
goto err_unreg_cec;
|
||||
}
|
||||
|
||||
|
|
|
@ -546,30 +546,24 @@ static inline bool is_digital_input(struct v4l2_subdev *sd)
|
|||
|
||||
static const struct v4l2_dv_timings_cap adv7842_timings_cap_analog = {
|
||||
.type = V4L2_DV_BT_656_1120,
|
||||
.bt = {
|
||||
.max_width = 1920,
|
||||
.max_height = 1200,
|
||||
.min_pixelclock = 25000000,
|
||||
.max_pixelclock = 170000000,
|
||||
.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
/* keep this initialization for compatibility with GCC < 4.4.6 */
|
||||
.reserved = { 0 },
|
||||
V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 170000000,
|
||||
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
|
||||
.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
|
||||
V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
|
||||
},
|
||||
V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
|
||||
V4L2_DV_BT_CAP_CUSTOM)
|
||||
};
|
||||
|
||||
static const struct v4l2_dv_timings_cap adv7842_timings_cap_digital = {
|
||||
.type = V4L2_DV_BT_656_1120,
|
||||
.bt = {
|
||||
.max_width = 1920,
|
||||
.max_height = 1200,
|
||||
.min_pixelclock = 25000000,
|
||||
.max_pixelclock = 225000000,
|
||||
.standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
/* keep this initialization for compatibility with GCC < 4.4.6 */
|
||||
.reserved = { 0 },
|
||||
V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1200, 25000000, 225000000,
|
||||
V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
|
||||
V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
|
||||
.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE |
|
||||
V4L2_DV_BT_CAP_REDUCED_BLANKING | V4L2_DV_BT_CAP_CUSTOM,
|
||||
},
|
||||
V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_REDUCED_BLANKING |
|
||||
V4L2_DV_BT_CAP_CUSTOM)
|
||||
};
|
||||
|
||||
static inline const struct v4l2_dv_timings_cap *
|
||||
|
|
|
@ -46,14 +46,10 @@ struct ths8200_state {
|
|||
|
||||
static const struct v4l2_dv_timings_cap ths8200_timings_cap = {
|
||||
.type = V4L2_DV_BT_656_1120,
|
||||
.bt = {
|
||||
.max_width = 1920,
|
||||
.max_height = 1080,
|
||||
.min_pixelclock = 25000000,
|
||||
.max_pixelclock = 148500000,
|
||||
.standards = V4L2_DV_BT_STD_CEA861,
|
||||
.capabilities = V4L2_DV_BT_CAP_PROGRESSIVE,
|
||||
},
|
||||
/* keep this initialization for compatibility with GCC < 4.4.6 */
|
||||
.reserved = { 0 },
|
||||
V4L2_INIT_BT_TIMINGS(0, 1920, 0, 1080, 25000000, 148500000,
|
||||
V4L2_DV_BT_STD_CEA861, V4L2_DV_BT_CAP_PROGRESSIVE)
|
||||
};
|
||||
|
||||
static inline struct ths8200_state *to_state(struct v4l2_subdev *sd)
|
||||
|
|
|
@ -1455,6 +1455,7 @@ static int video_release(struct file *file)
|
|||
|
||||
/* stop video capture */
|
||||
if (res_check(fh, RESOURCE_VIDEO)) {
|
||||
pm_qos_remove_request(&dev->qos_request);
|
||||
videobuf_streamoff(&fh->cap);
|
||||
res_free(dev,fh,RESOURCE_VIDEO);
|
||||
}
|
||||
|
|
|
@ -1423,6 +1423,7 @@ static int s5p_jpeg_probe(struct platform_device *pdev)
|
|||
jpeg->vfd_decoder->release = video_device_release;
|
||||
jpeg->vfd_decoder->lock = &jpeg->lock;
|
||||
jpeg->vfd_decoder->v4l2_dev = &jpeg->v4l2_dev;
|
||||
jpeg->vfd_decoder->vfl_dir = VFL_DIR_M2M;
|
||||
|
||||
ret = video_register_device(jpeg->vfd_decoder, VFL_TYPE_GRABBER, -1);
|
||||
if (ret) {
|
||||
|
|
|
@ -776,7 +776,7 @@ static int sh_vou_try_fmt_vid_out(struct file *file, void *priv,
|
|||
v4l_bound_align_image(&pix->width, 0, VOU_MAX_IMAGE_WIDTH, 1,
|
||||
&pix->height, 0, VOU_MAX_IMAGE_HEIGHT, 1, 0);
|
||||
|
||||
for (i = 0; ARRAY_SIZE(vou_fmt); i++)
|
||||
for (i = 0; i < ARRAY_SIZE(vou_fmt); i++)
|
||||
if (vou_fmt[i].pfmt == pix->pixelformat)
|
||||
return 0;
|
||||
|
||||
|
|
|
@ -266,7 +266,6 @@ static void mx3_videobuf_queue(struct vb2_buffer *vb)
|
|||
struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
|
||||
struct idmac_video_param *video = &ichan->params.video;
|
||||
const struct soc_mbus_pixelfmt *host_fmt = icd->current_fmt->host_fmt;
|
||||
unsigned long flags;
|
||||
dma_cookie_t cookie;
|
||||
size_t new_size;
|
||||
|
||||
|
@ -328,7 +327,7 @@ static void mx3_videobuf_queue(struct vb2_buffer *vb)
|
|||
memset(vb2_plane_vaddr(vb, 0), 0xaa, vb2_get_plane_payload(vb, 0));
|
||||
#endif
|
||||
|
||||
spin_lock_irqsave(&mx3_cam->lock, flags);
|
||||
spin_lock_irq(&mx3_cam->lock);
|
||||
list_add_tail(&buf->queue, &mx3_cam->capture);
|
||||
|
||||
if (!mx3_cam->active)
|
||||
|
@ -351,7 +350,7 @@ static void mx3_videobuf_queue(struct vb2_buffer *vb)
|
|||
if (mx3_cam->active == buf)
|
||||
mx3_cam->active = NULL;
|
||||
|
||||
spin_unlock_irqrestore(&mx3_cam->lock, flags);
|
||||
spin_unlock_irq(&mx3_cam->lock);
|
||||
error:
|
||||
vb2_buffer_done(vb, VB2_BUF_STATE_ERROR);
|
||||
}
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
*/
|
||||
|
||||
#include "e4000_priv.h"
|
||||
#include <linux/math64.h>
|
||||
|
||||
/* write multiple registers */
|
||||
static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
|
||||
|
@ -233,7 +234,7 @@ static int e4000_set_params(struct dvb_frontend *fe)
|
|||
* or more.
|
||||
*/
|
||||
f_vco = c->frequency * e4000_pll_lut[i].mul;
|
||||
sigma_delta = 0x10000UL * (f_vco % priv->cfg->clock) / priv->cfg->clock;
|
||||
sigma_delta = div_u64(0x10000ULL * (f_vco % priv->cfg->clock), priv->cfg->clock);
|
||||
buf[0] = f_vco / priv->cfg->clock;
|
||||
buf[1] = (sigma_delta >> 0) & 0xff;
|
||||
buf[2] = (sigma_delta >> 8) & 0xff;
|
||||
|
|
|
@ -111,6 +111,13 @@ static const struct dmi_system_id stk_upside_down_dmi_table[] = {
|
|||
DMI_MATCH(DMI_PRODUCT_NAME, "F3JC")
|
||||
}
|
||||
},
|
||||
{
|
||||
.ident = "T12Rg-H",
|
||||
.matches = {
|
||||
DMI_MATCH(DMI_SYS_VENDOR, "HCL Infosystems Limited"),
|
||||
DMI_MATCH(DMI_PRODUCT_NAME, "T12Rg-H")
|
||||
}
|
||||
},
|
||||
{}
|
||||
};
|
||||
|
||||
|
|
|
@ -2090,6 +2090,15 @@ static struct usb_device_id uvc_ids[] = {
|
|||
.bInterfaceSubClass = 1,
|
||||
.bInterfaceProtocol = 0,
|
||||
.driver_info = UVC_QUIRK_PROBE_MINMAX },
|
||||
/* Microsoft Lifecam NX-3000 */
|
||||
{ .match_flags = USB_DEVICE_ID_MATCH_DEVICE
|
||||
| USB_DEVICE_ID_MATCH_INT_INFO,
|
||||
.idVendor = 0x045e,
|
||||
.idProduct = 0x0721,
|
||||
.bInterfaceClass = USB_CLASS_VIDEO,
|
||||
.bInterfaceSubClass = 1,
|
||||
.bInterfaceProtocol = 0,
|
||||
.driver_info = UVC_QUIRK_PROBE_DEF },
|
||||
/* Microsoft Lifecam VX-7000 */
|
||||
{ .match_flags = USB_DEVICE_ID_MATCH_DEVICE
|
||||
| USB_DEVICE_ID_MATCH_INT_INFO,
|
||||
|
@ -2174,6 +2183,15 @@ static struct usb_device_id uvc_ids[] = {
|
|||
.bInterfaceSubClass = 1,
|
||||
.bInterfaceProtocol = 0,
|
||||
.driver_info = UVC_QUIRK_PROBE_DEF },
|
||||
/* Dell SP2008WFP Monitor */
|
||||
{ .match_flags = USB_DEVICE_ID_MATCH_DEVICE
|
||||
| USB_DEVICE_ID_MATCH_INT_INFO,
|
||||
.idVendor = 0x05a9,
|
||||
.idProduct = 0x2641,
|
||||
.bInterfaceClass = USB_CLASS_VIDEO,
|
||||
.bInterfaceSubClass = 1,
|
||||
.bInterfaceProtocol = 0,
|
||||
.driver_info = UVC_QUIRK_PROBE_DEF },
|
||||
/* Dell Alienware X51 */
|
||||
{ .match_flags = USB_DEVICE_ID_MATCH_DEVICE
|
||||
| USB_DEVICE_ID_MATCH_INT_INFO,
|
||||
|
|
|
@ -353,7 +353,9 @@ static int __verify_length(struct vb2_buffer *vb, const struct v4l2_buffer *b)
|
|||
|
||||
if (b->m.planes[plane].bytesused > length)
|
||||
return -EINVAL;
|
||||
if (b->m.planes[plane].data_offset >=
|
||||
|
||||
if (b->m.planes[plane].data_offset > 0 &&
|
||||
b->m.planes[plane].data_offset >=
|
||||
b->m.planes[plane].bytesused)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
|
|
@ -423,6 +423,39 @@ static inline int vma_is_io(struct vm_area_struct *vma)
|
|||
return !!(vma->vm_flags & (VM_IO | VM_PFNMAP));
|
||||
}
|
||||
|
||||
static int vb2_dc_get_user_pfn(unsigned long start, int n_pages,
|
||||
struct vm_area_struct *vma, unsigned long *res)
|
||||
{
|
||||
unsigned long pfn, start_pfn, prev_pfn;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
||||
if (!vma_is_io(vma))
|
||||
return -EFAULT;
|
||||
|
||||
ret = follow_pfn(vma, start, &pfn);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
start_pfn = pfn;
|
||||
start += PAGE_SIZE;
|
||||
|
||||
for (i = 1; i < n_pages; ++i, start += PAGE_SIZE) {
|
||||
prev_pfn = pfn;
|
||||
ret = follow_pfn(vma, start, &pfn);
|
||||
|
||||
if (ret) {
|
||||
pr_err("no page for address %lu\n", start);
|
||||
return ret;
|
||||
}
|
||||
if (pfn != prev_pfn + 1)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
*res = start_pfn;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int vb2_dc_get_user_pages(unsigned long start, struct page **pages,
|
||||
int n_pages, struct vm_area_struct *vma, int write)
|
||||
{
|
||||
|
@ -433,6 +466,9 @@ static int vb2_dc_get_user_pages(unsigned long start, struct page **pages,
|
|||
unsigned long pfn;
|
||||
int ret = follow_pfn(vma, start, &pfn);
|
||||
|
||||
if (!pfn_valid(pfn))
|
||||
return -EINVAL;
|
||||
|
||||
if (ret) {
|
||||
pr_err("no page for address %lu\n", start);
|
||||
return ret;
|
||||
|
@ -468,16 +504,49 @@ static void vb2_dc_put_userptr(void *buf_priv)
|
|||
struct vb2_dc_buf *buf = buf_priv;
|
||||
struct sg_table *sgt = buf->dma_sgt;
|
||||
|
||||
dma_unmap_sg(buf->dev, sgt->sgl, sgt->orig_nents, buf->dma_dir);
|
||||
if (!vma_is_io(buf->vma))
|
||||
vb2_dc_sgt_foreach_page(sgt, vb2_dc_put_dirty_page);
|
||||
if (sgt) {
|
||||
dma_unmap_sg(buf->dev, sgt->sgl, sgt->orig_nents, buf->dma_dir);
|
||||
if (!vma_is_io(buf->vma))
|
||||
vb2_dc_sgt_foreach_page(sgt, vb2_dc_put_dirty_page);
|
||||
|
||||
sg_free_table(sgt);
|
||||
kfree(sgt);
|
||||
sg_free_table(sgt);
|
||||
kfree(sgt);
|
||||
}
|
||||
vb2_put_vma(buf->vma);
|
||||
kfree(buf);
|
||||
}
|
||||
|
||||
/*
|
||||
* For some kind of reserved memory there might be no struct page available,
|
||||
* so all that can be done to support such 'pages' is to try to convert
|
||||
* pfn to dma address or at the last resort just assume that
|
||||
* dma address == physical address (like it has been assumed in earlier version
|
||||
* of videobuf2-dma-contig
|
||||
*/
|
||||
|
||||
#ifdef __arch_pfn_to_dma
|
||||
static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
|
||||
{
|
||||
return (dma_addr_t)__arch_pfn_to_dma(dev, pfn);
|
||||
}
|
||||
#elif defined(__pfn_to_bus)
|
||||
static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
|
||||
{
|
||||
return (dma_addr_t)__pfn_to_bus(pfn);
|
||||
}
|
||||
#elif defined(__pfn_to_phys)
|
||||
static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
|
||||
{
|
||||
return (dma_addr_t)__pfn_to_phys(pfn);
|
||||
}
|
||||
#else
|
||||
static inline dma_addr_t vb2_dc_pfn_to_dma(struct device *dev, unsigned long pfn)
|
||||
{
|
||||
/* really, we cannot do anything better at this point */
|
||||
return (dma_addr_t)(pfn) << PAGE_SHIFT;
|
||||
}
|
||||
#endif
|
||||
|
||||
static void *vb2_dc_get_userptr(void *alloc_ctx, unsigned long vaddr,
|
||||
unsigned long size, int write)
|
||||
{
|
||||
|
@ -548,6 +617,14 @@ static void *vb2_dc_get_userptr(void *alloc_ctx, unsigned long vaddr,
|
|||
/* extract page list from userspace mapping */
|
||||
ret = vb2_dc_get_user_pages(start, pages, n_pages, vma, write);
|
||||
if (ret) {
|
||||
unsigned long pfn;
|
||||
if (vb2_dc_get_user_pfn(start, n_pages, vma, &pfn) == 0) {
|
||||
buf->dma_addr = vb2_dc_pfn_to_dma(buf->dev, pfn);
|
||||
buf->size = size;
|
||||
kfree(pages);
|
||||
return buf;
|
||||
}
|
||||
|
||||
pr_err("failed to get user pages\n");
|
||||
goto fail_vma;
|
||||
}
|
||||
|
|
|
@ -349,7 +349,7 @@ static int legacy_set_geometry(struct gpmi_nand_data *this)
|
|||
|
||||
int common_nfc_set_geometry(struct gpmi_nand_data *this)
|
||||
{
|
||||
return set_geometry_by_ecc_info(this) ? 0 : legacy_set_geometry(this);
|
||||
return legacy_set_geometry(this);
|
||||
}
|
||||
|
||||
struct dma_chan *get_dma_chan(struct gpmi_nand_data *this)
|
||||
|
|
|
@ -1320,7 +1320,12 @@ static int pxa3xx_nand_probe(struct platform_device *pdev)
|
|||
for (cs = 0; cs < pdata->num_cs; cs++) {
|
||||
struct mtd_info *mtd = info->host[cs]->mtd;
|
||||
|
||||
mtd->name = pdev->name;
|
||||
/*
|
||||
* The mtd name matches the one used in 'mtdparts' kernel
|
||||
* parameter. This name cannot be changed or otherwise
|
||||
* user's mtd partitions configuration would get broken.
|
||||
*/
|
||||
mtd->name = "pxa3xx_nand-0";
|
||||
info->cs = cs;
|
||||
ret = pxa3xx_nand_scan(mtd);
|
||||
if (ret) {
|
||||
|
|
|
@ -1405,10 +1405,10 @@ static int at91_can_remove(struct platform_device *pdev)
|
|||
|
||||
static const struct platform_device_id at91_can_id_table[] = {
|
||||
{
|
||||
.name = "at91_can",
|
||||
.name = "at91sam9x5_can",
|
||||
.driver_data = (kernel_ulong_t)&at91_at91sam9x5_data,
|
||||
}, {
|
||||
.name = "at91sam9x5_can",
|
||||
.name = "at91_can",
|
||||
.driver_data = (kernel_ulong_t)&at91_at91sam9263_data,
|
||||
}, {
|
||||
/* sentinel */
|
||||
|
|
|
@ -705,14 +705,14 @@ static size_t can_get_size(const struct net_device *dev)
|
|||
size_t size;
|
||||
|
||||
size = nla_total_size(sizeof(u32)); /* IFLA_CAN_STATE */
|
||||
size += sizeof(struct can_ctrlmode); /* IFLA_CAN_CTRLMODE */
|
||||
size += nla_total_size(sizeof(struct can_ctrlmode)); /* IFLA_CAN_CTRLMODE */
|
||||
size += nla_total_size(sizeof(u32)); /* IFLA_CAN_RESTART_MS */
|
||||
size += sizeof(struct can_bittiming); /* IFLA_CAN_BITTIMING */
|
||||
size += sizeof(struct can_clock); /* IFLA_CAN_CLOCK */
|
||||
size += nla_total_size(sizeof(struct can_bittiming)); /* IFLA_CAN_BITTIMING */
|
||||
size += nla_total_size(sizeof(struct can_clock)); /* IFLA_CAN_CLOCK */
|
||||
if (priv->do_get_berr_counter) /* IFLA_CAN_BERR_COUNTER */
|
||||
size += sizeof(struct can_berr_counter);
|
||||
size += nla_total_size(sizeof(struct can_berr_counter));
|
||||
if (priv->bittiming_const) /* IFLA_CAN_BITTIMING_CONST */
|
||||
size += sizeof(struct can_bittiming_const);
|
||||
size += nla_total_size(sizeof(struct can_bittiming_const));
|
||||
|
||||
return size;
|
||||
}
|
||||
|
|
|
@ -62,7 +62,7 @@
|
|||
#define FLEXCAN_MCR_BCC BIT(16)
|
||||
#define FLEXCAN_MCR_LPRIO_EN BIT(13)
|
||||
#define FLEXCAN_MCR_AEN BIT(12)
|
||||
#define FLEXCAN_MCR_MAXMB(x) ((x) & 0xf)
|
||||
#define FLEXCAN_MCR_MAXMB(x) ((x) & 0x1f)
|
||||
#define FLEXCAN_MCR_IDAM_A (0 << 8)
|
||||
#define FLEXCAN_MCR_IDAM_B (1 << 8)
|
||||
#define FLEXCAN_MCR_IDAM_C (2 << 8)
|
||||
|
@ -735,9 +735,11 @@ static int flexcan_chip_start(struct net_device *dev)
|
|||
*
|
||||
*/
|
||||
reg_mcr = flexcan_read(®s->mcr);
|
||||
reg_mcr &= ~FLEXCAN_MCR_MAXMB(0xff);
|
||||
reg_mcr |= FLEXCAN_MCR_FRZ | FLEXCAN_MCR_FEN | FLEXCAN_MCR_HALT |
|
||||
FLEXCAN_MCR_SUPV | FLEXCAN_MCR_WRN_EN |
|
||||
FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS;
|
||||
FLEXCAN_MCR_IDAM_C | FLEXCAN_MCR_SRX_DIS |
|
||||
FLEXCAN_MCR_MAXMB(FLEXCAN_TX_BUF_ID);
|
||||
netdev_dbg(dev, "%s: writing mcr=0x%08x", __func__, reg_mcr);
|
||||
flexcan_write(reg_mcr, ®s->mcr);
|
||||
|
||||
|
@ -771,6 +773,10 @@ static int flexcan_chip_start(struct net_device *dev)
|
|||
netdev_dbg(dev, "%s: writing ctrl=0x%08x", __func__, reg_ctrl);
|
||||
flexcan_write(reg_ctrl, ®s->ctrl);
|
||||
|
||||
/* Abort any pending TX, mark Mailbox as INACTIVE */
|
||||
flexcan_write(FLEXCAN_MB_CNT_CODE(0x4),
|
||||
®s->cantxfg[FLEXCAN_TX_BUF_ID].can_ctrl);
|
||||
|
||||
/* acceptance mask/acceptance code (accept everything) */
|
||||
flexcan_write(0x0, ®s->rxgmask);
|
||||
flexcan_write(0x0, ®s->rx14mask);
|
||||
|
@ -979,9 +985,9 @@ static void unregister_flexcandev(struct net_device *dev)
|
|||
}
|
||||
|
||||
static const struct of_device_id flexcan_of_match[] = {
|
||||
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
|
||||
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
|
||||
{ .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
|
||||
{ .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
|
||||
{ .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
|
||||
{ /* sentinel */ },
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, flexcan_of_match);
|
||||
|
|
|
@ -1197,8 +1197,9 @@ union cdu_context {
|
|||
/* TM (timers) host DB constants */
|
||||
#define TM_ILT_PAGE_SZ_HW 0
|
||||
#define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
|
||||
/* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
|
||||
#define TM_CONN_NUM 1024
|
||||
#define TM_CONN_NUM (BNX2X_FIRST_VF_CID + \
|
||||
BNX2X_VF_CIDS + \
|
||||
CNIC_ISCSI_CID_MAX)
|
||||
#define TM_ILT_SZ (8 * TM_CONN_NUM)
|
||||
#define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
|
||||
|
||||
|
@ -1527,7 +1528,6 @@ struct bnx2x {
|
|||
#define PCI_32BIT_FLAG (1 << 1)
|
||||
#define ONE_PORT_FLAG (1 << 2)
|
||||
#define NO_WOL_FLAG (1 << 3)
|
||||
#define USING_DAC_FLAG (1 << 4)
|
||||
#define USING_MSIX_FLAG (1 << 5)
|
||||
#define USING_MSI_FLAG (1 << 6)
|
||||
#define DISABLE_MSI_FLAG (1 << 7)
|
||||
|
@ -1621,7 +1621,7 @@ struct bnx2x {
|
|||
u16 rx_ticks_int;
|
||||
u16 rx_ticks;
|
||||
/* Maximal coalescing timeout in us */
|
||||
#define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
|
||||
#define BNX2X_MAX_COALESCE_TOUT (0xff*BNX2X_BTR)
|
||||
|
||||
u32 lin_cnt;
|
||||
|
||||
|
@ -2072,7 +2072,8 @@ u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
|
|||
|
||||
void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
|
||||
u8 src_type, u8 dst_type);
|
||||
int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
|
||||
int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
|
||||
u32 *comp);
|
||||
|
||||
/* FLR related routines */
|
||||
u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
|
||||
|
@ -2498,4 +2499,8 @@ enum bnx2x_pci_bus_speed {
|
|||
};
|
||||
|
||||
void bnx2x_set_local_cmng(struct bnx2x *bp);
|
||||
|
||||
#define MCPR_SCRATCH_BASE(bp) \
|
||||
(CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
|
||||
|
||||
#endif /* bnx2x.h */
|
||||
|
|
|
@ -681,6 +681,7 @@ static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
|
|||
}
|
||||
}
|
||||
#endif
|
||||
skb_record_rx_queue(skb, fp->rx_queue);
|
||||
napi_gro_receive(&fp->napi, skb);
|
||||
}
|
||||
|
||||
|
|
|
@ -891,17 +891,8 @@ static void bnx2x_get_regs(struct net_device *dev,
|
|||
* will re-enable parity attentions right after the dump.
|
||||
*/
|
||||
|
||||
/* Disable parity on path 0 */
|
||||
bnx2x_pretend_func(bp, 0);
|
||||
bnx2x_disable_blocks_parity(bp);
|
||||
|
||||
/* Disable parity on path 1 */
|
||||
bnx2x_pretend_func(bp, 1);
|
||||
bnx2x_disable_blocks_parity(bp);
|
||||
|
||||
/* Return to current function */
|
||||
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
|
||||
|
||||
dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
|
||||
dump_hdr.preset = DUMP_ALL_PRESETS;
|
||||
dump_hdr.version = BNX2X_DUMP_VERSION;
|
||||
|
@ -928,18 +919,9 @@ static void bnx2x_get_regs(struct net_device *dev,
|
|||
/* Actually read the registers */
|
||||
__bnx2x_get_regs(bp, p);
|
||||
|
||||
/* Re-enable parity attentions on path 0 */
|
||||
bnx2x_pretend_func(bp, 0);
|
||||
/* Re-enable parity attentions */
|
||||
bnx2x_clear_blocks_parity(bp);
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
|
||||
/* Re-enable parity attentions on path 1 */
|
||||
bnx2x_pretend_func(bp, 1);
|
||||
bnx2x_clear_blocks_parity(bp);
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
|
||||
/* Return to current function */
|
||||
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
|
||||
}
|
||||
|
||||
static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
|
||||
|
@ -993,17 +975,8 @@ static int bnx2x_get_dump_data(struct net_device *dev,
|
|||
* will re-enable parity attentions right after the dump.
|
||||
*/
|
||||
|
||||
/* Disable parity on path 0 */
|
||||
bnx2x_pretend_func(bp, 0);
|
||||
bnx2x_disable_blocks_parity(bp);
|
||||
|
||||
/* Disable parity on path 1 */
|
||||
bnx2x_pretend_func(bp, 1);
|
||||
bnx2x_disable_blocks_parity(bp);
|
||||
|
||||
/* Return to current function */
|
||||
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
|
||||
|
||||
dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
|
||||
dump_hdr.preset = bp->dump_preset_idx;
|
||||
dump_hdr.version = BNX2X_DUMP_VERSION;
|
||||
|
@ -1032,19 +1005,10 @@ static int bnx2x_get_dump_data(struct net_device *dev,
|
|||
/* Actually read the registers */
|
||||
__bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
|
||||
|
||||
/* Re-enable parity attentions on path 0 */
|
||||
bnx2x_pretend_func(bp, 0);
|
||||
/* Re-enable parity attentions */
|
||||
bnx2x_clear_blocks_parity(bp);
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
|
||||
/* Re-enable parity attentions on path 1 */
|
||||
bnx2x_pretend_func(bp, 1);
|
||||
bnx2x_clear_blocks_parity(bp);
|
||||
bnx2x_enable_blocks_parity(bp);
|
||||
|
||||
/* Return to current function */
|
||||
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -640,23 +640,35 @@ static const struct {
|
|||
* [30] MCP Latched ump_tx_parity
|
||||
* [31] MCP Latched scpad_parity
|
||||
*/
|
||||
#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
|
||||
#define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \
|
||||
(AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY)
|
||||
|
||||
#define MISC_AEU_ENABLE_MCP_PRTY_BITS \
|
||||
(MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \
|
||||
AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
|
||||
|
||||
/* Below registers control the MCP parity attention output. When
|
||||
* MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are
|
||||
* enabled, when cleared - disabled.
|
||||
*/
|
||||
static const u32 mcp_attn_ctl_regs[] = {
|
||||
MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
|
||||
MISC_REG_AEU_ENABLE4_NIG_0,
|
||||
MISC_REG_AEU_ENABLE4_PXP_0,
|
||||
MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
|
||||
MISC_REG_AEU_ENABLE4_NIG_1,
|
||||
MISC_REG_AEU_ENABLE4_PXP_1
|
||||
static const struct {
|
||||
u32 addr;
|
||||
u32 bits;
|
||||
} mcp_attn_ctl_regs[] = {
|
||||
{ MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0,
|
||||
MISC_AEU_ENABLE_MCP_PRTY_BITS },
|
||||
{ MISC_REG_AEU_ENABLE4_NIG_0,
|
||||
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
|
||||
{ MISC_REG_AEU_ENABLE4_PXP_0,
|
||||
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
|
||||
{ MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0,
|
||||
MISC_AEU_ENABLE_MCP_PRTY_BITS },
|
||||
{ MISC_REG_AEU_ENABLE4_NIG_1,
|
||||
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS },
|
||||
{ MISC_REG_AEU_ENABLE4_PXP_1,
|
||||
MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }
|
||||
};
|
||||
|
||||
static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
|
||||
|
@ -665,14 +677,14 @@ static inline void bnx2x_set_mcp_parity(struct bnx2x *bp, u8 enable)
|
|||
u32 reg_val;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(mcp_attn_ctl_regs); i++) {
|
||||
reg_val = REG_RD(bp, mcp_attn_ctl_regs[i]);
|
||||
reg_val = REG_RD(bp, mcp_attn_ctl_regs[i].addr);
|
||||
|
||||
if (enable)
|
||||
reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS;
|
||||
reg_val |= mcp_attn_ctl_regs[i].bits;
|
||||
else
|
||||
reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS;
|
||||
reg_val &= ~mcp_attn_ctl_regs[i].bits;
|
||||
|
||||
REG_WR(bp, mcp_attn_ctl_regs[i], reg_val);
|
||||
REG_WR(bp, mcp_attn_ctl_regs[i].addr, reg_val);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -503,9 +503,9 @@ void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
|
|||
}
|
||||
|
||||
/* issue a dmae command over the init-channel and wait for completion */
|
||||
int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
|
||||
int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
|
||||
u32 *comp)
|
||||
{
|
||||
u32 *wb_comp = bnx2x_sp(bp, wb_comp);
|
||||
int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
|
||||
int rc = 0;
|
||||
|
||||
|
@ -518,14 +518,14 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
|
|||
spin_lock_bh(&bp->dmae_lock);
|
||||
|
||||
/* reset completion */
|
||||
*wb_comp = 0;
|
||||
*comp = 0;
|
||||
|
||||
/* post the command on the channel used for initializations */
|
||||
bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
|
||||
|
||||
/* wait for completion */
|
||||
udelay(5);
|
||||
while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
|
||||
while ((*comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
|
||||
|
||||
if (!cnt ||
|
||||
(bp->recovery_state != BNX2X_RECOVERY_DONE &&
|
||||
|
@ -537,7 +537,7 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
|
|||
cnt--;
|
||||
udelay(50);
|
||||
}
|
||||
if (*wb_comp & DMAE_PCI_ERR_FLAG) {
|
||||
if (*comp & DMAE_PCI_ERR_FLAG) {
|
||||
BNX2X_ERR("DMAE PCI error!\n");
|
||||
rc = DMAE_PCI_ERROR;
|
||||
}
|
||||
|
@ -574,7 +574,7 @@ void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
|
|||
dmae.len = len32;
|
||||
|
||||
/* issue the command and wait for completion */
|
||||
rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
|
||||
rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
|
||||
if (rc) {
|
||||
BNX2X_ERR("DMAE returned failure %d\n", rc);
|
||||
bnx2x_panic();
|
||||
|
@ -611,7 +611,7 @@ void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
|
|||
dmae.len = len32;
|
||||
|
||||
/* issue the command and wait for completion */
|
||||
rc = bnx2x_issue_dmae_with_comp(bp, &dmae);
|
||||
rc = bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
|
||||
if (rc) {
|
||||
BNX2X_ERR("DMAE returned failure %d\n", rc);
|
||||
bnx2x_panic();
|
||||
|
@ -751,6 +751,10 @@ static int bnx2x_mc_assert(struct bnx2x *bp)
|
|||
return rc;
|
||||
}
|
||||
|
||||
#define MCPR_TRACE_BUFFER_SIZE (0x800)
|
||||
#define SCRATCH_BUFFER_SIZE(bp) \
|
||||
(CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
|
||||
|
||||
void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
|
||||
{
|
||||
u32 addr, val;
|
||||
|
@ -775,7 +779,17 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
|
|||
trace_shmem_base = bp->common.shmem_base;
|
||||
else
|
||||
trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
|
||||
addr = trace_shmem_base - 0x800;
|
||||
|
||||
/* sanity */
|
||||
if (trace_shmem_base < MCPR_SCRATCH_BASE(bp) + MCPR_TRACE_BUFFER_SIZE ||
|
||||
trace_shmem_base >= MCPR_SCRATCH_BASE(bp) +
|
||||
SCRATCH_BUFFER_SIZE(bp)) {
|
||||
BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
|
||||
trace_shmem_base);
|
||||
return;
|
||||
}
|
||||
|
||||
addr = trace_shmem_base - MCPR_TRACE_BUFFER_SIZE;
|
||||
|
||||
/* validate TRCB signature */
|
||||
mark = REG_RD(bp, addr);
|
||||
|
@ -787,14 +801,17 @@ void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
|
|||
/* read cyclic buffer pointer */
|
||||
addr += 4;
|
||||
mark = REG_RD(bp, addr);
|
||||
mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
|
||||
+ ((mark + 0x3) & ~0x3) - 0x08000000;
|
||||
mark = MCPR_SCRATCH_BASE(bp) + ((mark + 0x3) & ~0x3) - 0x08000000;
|
||||
if (mark >= trace_shmem_base || mark < addr + 4) {
|
||||
BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
|
||||
return;
|
||||
}
|
||||
printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
|
||||
|
||||
printk("%s", lvl);
|
||||
|
||||
/* dump buffer after the mark */
|
||||
for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
|
||||
for (offset = mark; offset < trace_shmem_base; offset += 0x8*4) {
|
||||
for (word = 0; word < 8; word++)
|
||||
data[word] = htonl(REG_RD(bp, offset + 4*word));
|
||||
data[8] = 0x0;
|
||||
|
@ -4280,65 +4297,60 @@ static void _print_next_block(int idx, const char *blk)
|
|||
pr_cont("%s%s", idx ? ", " : "", blk);
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "BRB");
|
||||
res |= true; /* Each bit is real error! */
|
||||
|
||||
if (print) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "BRB");
|
||||
_print_parity(bp,
|
||||
BRB1_REG_BRB1_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PARSER");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"PARSER");
|
||||
_print_parity(bp, PRS_REG_PRS_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "TSDM");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "TSDM");
|
||||
_print_parity(bp,
|
||||
TSDM_REG_TSDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++,
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"SEARCHER");
|
||||
_print_parity(bp, SRC_REG_SRC_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "TCM");
|
||||
_print_parity(bp,
|
||||
TCM_REG_TCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "TSEMI");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "TCM");
|
||||
_print_parity(bp, TCM_REG_TCM_PRTY_STS);
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"TSEMI");
|
||||
_print_parity(bp,
|
||||
TSEM_REG_TSEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
TSEM_REG_TSEM_PRTY_STS_1);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XPB");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "XPB");
|
||||
_print_parity(bp, GRCBASE_XPB +
|
||||
PB_REG_PB_PRTY_STS);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear the bit */
|
||||
|
@ -4346,53 +4358,59 @@ static int bnx2x_check_blocks_with_parity0(struct bnx2x *bp, u32 sig,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool *global,
|
||||
static bool bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool *global,
|
||||
bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
res |= true; /* Each bit is real error! */
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PBF");
|
||||
_print_next_block((*par_num)++, "PBF");
|
||||
_print_parity(bp, PBF_REG_PBF_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "QM");
|
||||
_print_next_block((*par_num)++, "QM");
|
||||
_print_parity(bp, QM_REG_QM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "TM");
|
||||
_print_next_block((*par_num)++, "TM");
|
||||
_print_parity(bp, TM_REG_TM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XSDM");
|
||||
_print_next_block((*par_num)++, "XSDM");
|
||||
_print_parity(bp,
|
||||
XSDM_REG_XSDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XCM");
|
||||
_print_next_block((*par_num)++, "XCM");
|
||||
_print_parity(bp, XCM_REG_XCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "XSEMI");
|
||||
_print_next_block((*par_num)++,
|
||||
"XSEMI");
|
||||
_print_parity(bp,
|
||||
XSEM_REG_XSEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
|
@ -4401,7 +4419,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"DOORBELLQ");
|
||||
_print_parity(bp,
|
||||
DORQ_REG_DORQ_PRTY_STS);
|
||||
|
@ -4409,7 +4427,7 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "NIG");
|
||||
_print_next_block((*par_num)++, "NIG");
|
||||
if (CHIP_IS_E1x(bp)) {
|
||||
_print_parity(bp,
|
||||
NIG_REG_NIG_PRTY_STS);
|
||||
|
@ -4423,32 +4441,34 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"VAUX PCI CORE");
|
||||
*global = true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "DEBUG");
|
||||
_print_next_block((*par_num)++,
|
||||
"DEBUG");
|
||||
_print_parity(bp, DBG_REG_DBG_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "USDM");
|
||||
_print_next_block((*par_num)++, "USDM");
|
||||
_print_parity(bp,
|
||||
USDM_REG_USDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "UCM");
|
||||
_print_next_block((*par_num)++, "UCM");
|
||||
_print_parity(bp, UCM_REG_UCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "USEMI");
|
||||
_print_next_block((*par_num)++,
|
||||
"USEMI");
|
||||
_print_parity(bp,
|
||||
USEM_REG_USEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
|
@ -4457,21 +4477,21 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "UPB");
|
||||
_print_next_block((*par_num)++, "UPB");
|
||||
_print_parity(bp, GRCBASE_UPB +
|
||||
PB_REG_PB_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CSDM");
|
||||
_print_next_block((*par_num)++, "CSDM");
|
||||
_print_parity(bp,
|
||||
CSDM_REG_CSDM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CCM");
|
||||
_print_next_block((*par_num)++, "CCM");
|
||||
_print_parity(bp, CCM_REG_CCM_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
|
@ -4482,80 +4502,73 @@ static int bnx2x_check_blocks_with_parity1(struct bnx2x *bp, u32 sig,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CSEMI");
|
||||
res |= true; /* Each bit is real error! */
|
||||
if (print) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"CSEMI");
|
||||
_print_parity(bp,
|
||||
CSEM_REG_CSEM_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
CSEM_REG_CSEM_PRTY_STS_1);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PXP");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "PXP");
|
||||
_print_parity(bp, PXP_REG_PXP_PRTY_STS);
|
||||
_print_parity(bp,
|
||||
PXP2_REG_PXP2_PRTY_STS_0);
|
||||
_print_parity(bp,
|
||||
PXP2_REG_PXP2_PRTY_STS_1);
|
||||
}
|
||||
break;
|
||||
case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
"PXPPCICLOCKCLIENT");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CFC");
|
||||
break;
|
||||
case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"PXPPCICLOCKCLIENT");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "CFC");
|
||||
_print_parity(bp,
|
||||
CFC_REG_CFC_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "CDU");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "CDU");
|
||||
_print_parity(bp, CDU_REG_CDU_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "DMAE");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "DMAE");
|
||||
_print_parity(bp,
|
||||
DMAE_REG_DMAE_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "IGU");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "IGU");
|
||||
if (CHIP_IS_E1x(bp))
|
||||
_print_parity(bp,
|
||||
HC_REG_HC_PRTY_STS);
|
||||
else
|
||||
_print_parity(bp,
|
||||
IGU_REG_IGU_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "MISC");
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "MISC");
|
||||
_print_parity(bp,
|
||||
MISC_REG_MISC_PRTY_STS);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear the bit */
|
||||
|
@ -4563,40 +4576,49 @@ static int bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
|
||||
bool *global, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool *global,
|
||||
bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
bool res = false;
|
||||
u32 cur_bit;
|
||||
int i;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++, "MCP ROM");
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP ROM");
|
||||
*global = true;
|
||||
res |= true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP UMP RX");
|
||||
*global = true;
|
||||
res |= true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP UMP TX");
|
||||
*global = true;
|
||||
res |= true;
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
|
||||
if (print)
|
||||
_print_next_block(par_num++,
|
||||
_print_next_block((*par_num)++,
|
||||
"MCP SCPAD");
|
||||
*global = true;
|
||||
/* clear latched SCPAD PATIRY from MCP */
|
||||
REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL,
|
||||
1UL << 10);
|
||||
break;
|
||||
}
|
||||
|
||||
|
@ -4605,45 +4627,50 @@ static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
|
|||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static int bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
|
||||
int par_num, bool print)
|
||||
static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
|
||||
int *par_num, bool print)
|
||||
{
|
||||
int i = 0;
|
||||
u32 cur_bit = 0;
|
||||
u32 cur_bit;
|
||||
bool res;
|
||||
int i;
|
||||
|
||||
res = false;
|
||||
|
||||
for (i = 0; sig; i++) {
|
||||
cur_bit = ((u32)0x1 << i);
|
||||
cur_bit = (0x1UL << i);
|
||||
if (sig & cur_bit) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "PGLUE_B");
|
||||
res |= true; /* Each bit is real error! */
|
||||
if (print) {
|
||||
switch (cur_bit) {
|
||||
case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++,
|
||||
"PGLUE_B");
|
||||
_print_parity(bp,
|
||||
PGLUE_B_REG_PGLUE_B_PRTY_STS);
|
||||
}
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
|
||||
if (print) {
|
||||
_print_next_block(par_num++, "ATC");
|
||||
PGLUE_B_REG_PGLUE_B_PRTY_STS);
|
||||
break;
|
||||
case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
|
||||
_print_next_block((*par_num)++, "ATC");
|
||||
_print_parity(bp,
|
||||
ATC_REG_ATC_PRTY_STS);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
/* Clear the bit */
|
||||
sig &= ~cur_bit;
|
||||
}
|
||||
}
|
||||
|
||||
return par_num;
|
||||
return res;
|
||||
}
|
||||
|
||||
static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
|
||||
u32 *sig)
|
||||
{
|
||||
bool res = false;
|
||||
|
||||
if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
|
||||
(sig[1] & HW_PRTY_ASSERT_SET_1) ||
|
||||
(sig[2] & HW_PRTY_ASSERT_SET_2) ||
|
||||
|
@ -4660,23 +4687,22 @@ static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
|
|||
if (print)
|
||||
netdev_err(bp->dev,
|
||||
"Parity errors detected in blocks: ");
|
||||
par_num = bnx2x_check_blocks_with_parity0(bp,
|
||||
sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
|
||||
par_num = bnx2x_check_blocks_with_parity1(bp,
|
||||
sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
|
||||
par_num = bnx2x_check_blocks_with_parity2(bp,
|
||||
sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
|
||||
par_num = bnx2x_check_blocks_with_parity3(
|
||||
sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
|
||||
par_num = bnx2x_check_blocks_with_parity4(bp,
|
||||
sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
|
||||
res |= bnx2x_check_blocks_with_parity0(bp,
|
||||
sig[0] & HW_PRTY_ASSERT_SET_0, &par_num, print);
|
||||
res |= bnx2x_check_blocks_with_parity1(bp,
|
||||
sig[1] & HW_PRTY_ASSERT_SET_1, &par_num, global, print);
|
||||
res |= bnx2x_check_blocks_with_parity2(bp,
|
||||
sig[2] & HW_PRTY_ASSERT_SET_2, &par_num, print);
|
||||
res |= bnx2x_check_blocks_with_parity3(bp,
|
||||
sig[3] & HW_PRTY_ASSERT_SET_3, &par_num, global, print);
|
||||
res |= bnx2x_check_blocks_with_parity4(bp,
|
||||
sig[4] & HW_PRTY_ASSERT_SET_4, &par_num, print);
|
||||
|
||||
if (print)
|
||||
pr_cont("\n");
|
||||
}
|
||||
|
||||
return true;
|
||||
} else
|
||||
return false;
|
||||
return res;
|
||||
}
|
||||
|
||||
/**
|
||||
|
@ -7126,7 +7152,7 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
|||
int port = BP_PORT(bp);
|
||||
int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
|
||||
u32 low, high;
|
||||
u32 val;
|
||||
u32 val, reg;
|
||||
|
||||
DP(NETIF_MSG_HW, "starting port init port %d\n", port);
|
||||
|
||||
|
@ -7271,6 +7297,17 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)
|
|||
val |= CHIP_IS_E1(bp) ? 0 : 0x10;
|
||||
REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
|
||||
|
||||
/* SCPAD_PARITY should NOT trigger close the gates */
|
||||
reg = port ? MISC_REG_AEU_ENABLE4_NIG_1 : MISC_REG_AEU_ENABLE4_NIG_0;
|
||||
REG_WR(bp, reg,
|
||||
REG_RD(bp, reg) &
|
||||
~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
|
||||
|
||||
reg = port ? MISC_REG_AEU_ENABLE4_PXP_1 : MISC_REG_AEU_ENABLE4_PXP_0;
|
||||
REG_WR(bp, reg,
|
||||
REG_RD(bp, reg) &
|
||||
~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY);
|
||||
|
||||
bnx2x_init_block(bp, BLOCK_NIG, init_phase);
|
||||
|
||||
if (!CHIP_IS_E1x(bp)) {
|
||||
|
@ -11685,9 +11722,6 @@ static int bnx2x_init_bp(struct bnx2x *bp)
|
|||
static int bnx2x_open(struct net_device *dev)
|
||||
{
|
||||
struct bnx2x *bp = netdev_priv(dev);
|
||||
bool global = false;
|
||||
int other_engine = BP_PATH(bp) ? 0 : 1;
|
||||
bool other_load_status, load_status;
|
||||
int rc;
|
||||
|
||||
bp->stats_init = true;
|
||||
|
@ -11703,6 +11737,10 @@ static int bnx2x_open(struct net_device *dev)
|
|||
* Parity recovery is only relevant for PF driver.
|
||||
*/
|
||||
if (IS_PF(bp)) {
|
||||
int other_engine = BP_PATH(bp) ? 0 : 1;
|
||||
bool other_load_status, load_status;
|
||||
bool global = false;
|
||||
|
||||
other_load_status = bnx2x_get_load_status(bp, other_engine);
|
||||
load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
|
||||
if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
|
||||
|
@ -12080,7 +12118,6 @@ static int bnx2x_set_coherency_mask(struct bnx2x *bp)
|
|||
struct device *dev = &bp->pdev->dev;
|
||||
|
||||
if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
|
||||
bp->flags |= USING_DAC_FLAG;
|
||||
if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
|
||||
dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
|
||||
return -EIO;
|
||||
|
@ -12248,8 +12285,7 @@ static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
|
|||
NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
|
||||
|
||||
dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
|
||||
if (bp->flags & USING_DAC_FLAG)
|
||||
dev->features |= NETIF_F_HIGHDMA;
|
||||
dev->features |= NETIF_F_HIGHDMA;
|
||||
|
||||
/* Add Loopback capability to the device */
|
||||
dev->hw_features |= NETIF_F_LOOPBACK;
|
||||
|
@ -12612,24 +12648,24 @@ static int set_max_cos_est(int chip_id)
|
|||
return BNX2X_MULTI_TX_COS_E1X;
|
||||
case BCM57712:
|
||||
case BCM57712_MF:
|
||||
case BCM57712_VF:
|
||||
return BNX2X_MULTI_TX_COS_E2_E3A0;
|
||||
case BCM57800:
|
||||
case BCM57800_MF:
|
||||
case BCM57800_VF:
|
||||
case BCM57810:
|
||||
case BCM57810_MF:
|
||||
case BCM57840_4_10:
|
||||
case BCM57840_2_20:
|
||||
case BCM57840_O:
|
||||
case BCM57840_MFO:
|
||||
case BCM57810_VF:
|
||||
case BCM57840_MF:
|
||||
case BCM57840_VF:
|
||||
case BCM57811:
|
||||
case BCM57811_MF:
|
||||
case BCM57811_VF:
|
||||
return BNX2X_MULTI_TX_COS_E3B0;
|
||||
case BCM57712_VF:
|
||||
case BCM57800_VF:
|
||||
case BCM57810_VF:
|
||||
case BCM57840_VF:
|
||||
case BCM57811_VF:
|
||||
return 1;
|
||||
default:
|
||||
pr_err("Unknown board_type (%d), aborting\n", chip_id);
|
||||
|
|
|
@ -470,10 +470,10 @@ static int bnx2x_vfop_qdtor_cmd(struct bnx2x *bp,
|
|||
bnx2x_vfop_qdtor, cmd->done);
|
||||
return bnx2x_vfop_transition(bp, vf, bnx2x_vfop_qdtor,
|
||||
cmd->block);
|
||||
} else {
|
||||
BNX2X_ERR("VF[%d] failed to add a vfop\n", vf->abs_vfid);
|
||||
return -ENOMEM;
|
||||
}
|
||||
DP(BNX2X_MSG_IOV, "VF[%d] failed to add a vfop. rc %d\n",
|
||||
vf->abs_vfid, vfop->rc);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -3390,14 +3390,16 @@ int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
|
|||
rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_ETH_MAC, true);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to delete eth macs\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* remove existing uc list macs */
|
||||
rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, true);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to delete uc_list macs\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* configure the new mac to device */
|
||||
|
@ -3405,6 +3407,7 @@ int bnx2x_set_vf_mac(struct net_device *dev, int vfidx, u8 *mac)
|
|||
bnx2x_set_mac_one(bp, (u8 *)&bulletin->mac, mac_obj, true,
|
||||
BNX2X_ETH_MAC, &ramrod_flags);
|
||||
|
||||
out:
|
||||
bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_MAC);
|
||||
}
|
||||
|
||||
|
@ -3467,7 +3470,8 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
&ramrod_flags);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to delete vlans\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* send queue update ramrod to configure default vlan and silent
|
||||
|
@ -3501,7 +3505,8 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
|
||||
if (rc) {
|
||||
BNX2X_ERR("failed to configure vlan\n");
|
||||
return -EINVAL;
|
||||
rc = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* configure default vlan to vf queue and set silent
|
||||
|
@ -3519,18 +3524,18 @@ int bnx2x_set_vf_vlan(struct net_device *dev, int vfidx, u16 vlan, u8 qos)
|
|||
rc = bnx2x_queue_state_change(bp, &q_params);
|
||||
if (rc) {
|
||||
BNX2X_ERR("Failed to configure default VLAN\n");
|
||||
return rc;
|
||||
goto out;
|
||||
}
|
||||
|
||||
/* clear the flag indicating that this VF needs its vlan
|
||||
* (will only be set if the HV configured th Vlan before vf was
|
||||
* and we were called because the VF came up later
|
||||
* (will only be set if the HV configured the Vlan before vf was
|
||||
* up and we were called because the VF came up later
|
||||
*/
|
||||
out:
|
||||
vf->cfg_flags &= ~VF_CFG_VLAN;
|
||||
|
||||
bnx2x_unlock_vf_pf_channel(bp, vf, CHANNEL_TLV_PF_SET_VLAN);
|
||||
}
|
||||
return 0;
|
||||
return rc;
|
||||
}
|
||||
|
||||
/* crc is the first field in the bulletin board. Compute the crc over the
|
||||
|
|
|
@ -196,7 +196,7 @@ static void bnx2x_hw_stats_post(struct bnx2x *bp)
|
|||
|
||||
} else if (bp->func_stx) {
|
||||
*stats_comp = 0;
|
||||
bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
|
||||
bnx2x_issue_dmae_with_comp(bp, dmae, stats_comp);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -980,7 +980,7 @@ static int bnx2x_copy32_vf_dmae(struct bnx2x *bp, u8 from_vf,
|
|||
dmae.len = len32;
|
||||
|
||||
/* issue the command and wait for completion */
|
||||
return bnx2x_issue_dmae_with_comp(bp, &dmae);
|
||||
return bnx2x_issue_dmae_with_comp(bp, &dmae, bnx2x_sp(bp, wb_comp));
|
||||
}
|
||||
|
||||
static void bnx2x_vf_mbx_resp(struct bnx2x *bp, struct bnx2x_virtf *vf)
|
||||
|
|
|
@ -106,7 +106,6 @@
|
|||
#define XGMAC_DMA_HW_FEATURE 0x00000f58 /* Enabled Hardware Features */
|
||||
|
||||
#define XGMAC_ADDR_AE 0x80000000
|
||||
#define XGMAC_MAX_FILTER_ADDR 31
|
||||
|
||||
/* PMT Control and Status */
|
||||
#define XGMAC_PMT_POINTER_RESET 0x80000000
|
||||
|
@ -384,6 +383,7 @@ struct xgmac_priv {
|
|||
struct device *device;
|
||||
struct napi_struct napi;
|
||||
|
||||
int max_macs;
|
||||
struct xgmac_extra_stats xstats;
|
||||
|
||||
spinlock_t stats_lock;
|
||||
|
@ -1291,14 +1291,12 @@ static void xgmac_set_rx_mode(struct net_device *dev)
|
|||
netdev_dbg(priv->dev, "# mcasts %d, # unicast %d\n",
|
||||
netdev_mc_count(dev), netdev_uc_count(dev));
|
||||
|
||||
if (dev->flags & IFF_PROMISC) {
|
||||
writel(XGMAC_FRAME_FILTER_PR, ioaddr + XGMAC_FRAME_FILTER);
|
||||
return;
|
||||
}
|
||||
if (dev->flags & IFF_PROMISC)
|
||||
value |= XGMAC_FRAME_FILTER_PR;
|
||||
|
||||
memset(hash_filter, 0, sizeof(hash_filter));
|
||||
|
||||
if (netdev_uc_count(dev) > XGMAC_MAX_FILTER_ADDR) {
|
||||
if (netdev_uc_count(dev) > priv->max_macs) {
|
||||
use_hash = true;
|
||||
value |= XGMAC_FRAME_FILTER_HUC | XGMAC_FRAME_FILTER_HPF;
|
||||
}
|
||||
|
@ -1321,7 +1319,7 @@ static void xgmac_set_rx_mode(struct net_device *dev)
|
|||
goto out;
|
||||
}
|
||||
|
||||
if ((netdev_mc_count(dev) + reg - 1) > XGMAC_MAX_FILTER_ADDR) {
|
||||
if ((netdev_mc_count(dev) + reg - 1) > priv->max_macs) {
|
||||
use_hash = true;
|
||||
value |= XGMAC_FRAME_FILTER_HMC | XGMAC_FRAME_FILTER_HPF;
|
||||
} else {
|
||||
|
@ -1342,8 +1340,8 @@ static void xgmac_set_rx_mode(struct net_device *dev)
|
|||
}
|
||||
|
||||
out:
|
||||
for (i = reg; i < XGMAC_MAX_FILTER_ADDR; i++)
|
||||
xgmac_set_mac_addr(ioaddr, NULL, reg);
|
||||
for (i = reg; i <= priv->max_macs; i++)
|
||||
xgmac_set_mac_addr(ioaddr, NULL, i);
|
||||
for (i = 0; i < XGMAC_NUM_HASH; i++)
|
||||
writel(hash_filter[i], ioaddr + XGMAC_HASH(i));
|
||||
|
||||
|
@ -1761,6 +1759,13 @@ static int xgmac_probe(struct platform_device *pdev)
|
|||
uid = readl(priv->base + XGMAC_VERSION);
|
||||
netdev_info(ndev, "h/w version is 0x%x\n", uid);
|
||||
|
||||
/* Figure out how many valid mac address filter registers we have */
|
||||
writel(1, priv->base + XGMAC_ADDR_HIGH(31));
|
||||
if (readl(priv->base + XGMAC_ADDR_HIGH(31)) == 1)
|
||||
priv->max_macs = 31;
|
||||
else
|
||||
priv->max_macs = 7;
|
||||
|
||||
writel(0, priv->base + XGMAC_DMA_INTR_ENA);
|
||||
ndev->irq = platform_get_irq(pdev, 0);
|
||||
if (ndev->irq == -ENXIO) {
|
||||
|
|
|
@ -158,18 +158,6 @@ static inline board_info_t *to_dm9000_board(struct net_device *dev)
|
|||
|
||||
/* DM9000 network board routine ---------------------------- */
|
||||
|
||||
static void
|
||||
dm9000_reset(board_info_t * db)
|
||||
{
|
||||
dev_dbg(db->dev, "resetting device\n");
|
||||
|
||||
/* RESET device */
|
||||
writeb(DM9000_NCR, db->io_addr);
|
||||
udelay(200);
|
||||
writeb(NCR_RST, db->io_data);
|
||||
udelay(200);
|
||||
}
|
||||
|
||||
/*
|
||||
* Read a byte from I/O port
|
||||
*/
|
||||
|
@ -191,6 +179,27 @@ iow(board_info_t * db, int reg, int value)
|
|||
writeb(value, db->io_data);
|
||||
}
|
||||
|
||||
static void
|
||||
dm9000_reset(board_info_t *db)
|
||||
{
|
||||
dev_dbg(db->dev, "resetting device\n");
|
||||
|
||||
/* Reset DM9000, see DM9000 Application Notes V1.22 Jun 11, 2004 page 29
|
||||
* The essential point is that we have to do a double reset, and the
|
||||
* instruction is to set LBK into MAC internal loopback mode.
|
||||
*/
|
||||
iow(db, DM9000_NCR, 0x03);
|
||||
udelay(100); /* Application note says at least 20 us */
|
||||
if (ior(db, DM9000_NCR) & 1)
|
||||
dev_err(db->dev, "dm9000 did not respond to first reset\n");
|
||||
|
||||
iow(db, DM9000_NCR, 0);
|
||||
iow(db, DM9000_NCR, 0x03);
|
||||
udelay(100);
|
||||
if (ior(db, DM9000_NCR) & 1)
|
||||
dev_err(db->dev, "dm9000 did not respond to second reset\n");
|
||||
}
|
||||
|
||||
/* routines for sending block to chip */
|
||||
|
||||
static void dm9000_outblk_8bit(void __iomem *reg, void *data, int count)
|
||||
|
@ -744,15 +753,20 @@ static const struct ethtool_ops dm9000_ethtool_ops = {
|
|||
static void dm9000_show_carrier(board_info_t *db,
|
||||
unsigned carrier, unsigned nsr)
|
||||
{
|
||||
int lpa;
|
||||
struct net_device *ndev = db->ndev;
|
||||
struct mii_if_info *mii = &db->mii;
|
||||
unsigned ncr = dm9000_read_locked(db, DM9000_NCR);
|
||||
|
||||
if (carrier)
|
||||
dev_info(db->dev, "%s: link up, %dMbps, %s-duplex, no LPA\n",
|
||||
if (carrier) {
|
||||
lpa = mii->mdio_read(mii->dev, mii->phy_id, MII_LPA);
|
||||
dev_info(db->dev,
|
||||
"%s: link up, %dMbps, %s-duplex, lpa 0x%04X\n",
|
||||
ndev->name, (nsr & NSR_SPEED) ? 10 : 100,
|
||||
(ncr & NCR_FDX) ? "full" : "half");
|
||||
else
|
||||
(ncr & NCR_FDX) ? "full" : "half", lpa);
|
||||
} else {
|
||||
dev_info(db->dev, "%s: link down\n", ndev->name);
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
|
@ -890,9 +904,15 @@ dm9000_init_dm9000(struct net_device *dev)
|
|||
(dev->features & NETIF_F_RXCSUM) ? RCSR_CSUM : 0);
|
||||
|
||||
iow(db, DM9000_GPCR, GPCR_GEP_CNTL); /* Let GPIO0 output */
|
||||
iow(db, DM9000_GPR, 0);
|
||||
|
||||
dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET); /* PHY RESET */
|
||||
dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM); /* Init */
|
||||
/* If we are dealing with DM9000B, some extra steps are required: a
|
||||
* manual phy reset, and setting init params.
|
||||
*/
|
||||
if (db->type == TYPE_DM9000B) {
|
||||
dm9000_phy_write(dev, 0, MII_BMCR, BMCR_RESET);
|
||||
dm9000_phy_write(dev, 0, MII_DM_DSPCR, DSPCR_INIT_PARAM);
|
||||
}
|
||||
|
||||
ncr = (db->flags & DM9000_PLATF_EXT_PHY) ? NCR_EXT_PHY : 0;
|
||||
|
||||
|
|
|
@ -1198,7 +1198,6 @@ int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
|
|||
|
||||
if (lancer_chip(adapter)) {
|
||||
req->hdr.version = 1;
|
||||
req->if_id = cpu_to_le16(adapter->if_handle);
|
||||
} else if (BEx_chip(adapter)) {
|
||||
if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC)
|
||||
req->hdr.version = 2;
|
||||
|
@ -1206,6 +1205,8 @@ int be_cmd_txq_create(struct be_adapter *adapter, struct be_tx_obj *txo)
|
|||
req->hdr.version = 2;
|
||||
}
|
||||
|
||||
if (req->hdr.version > 0)
|
||||
req->if_id = cpu_to_le16(adapter->if_handle);
|
||||
req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
|
||||
req->ulp_num = BE_ULP1_NUM;
|
||||
req->type = BE_ETH_TX_RING_TYPE_STANDARD;
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue