drm/radeon/kms: Schedule host path read cache flush through the ring V2
R300 family will hard lockup if host path read cache flush is done through MMIO to HOST_PATH_CNTL. But scheduling same flush through ring seems harmless. This patch remove the hdp_flush callback and add a flush after each fence emission which means a flush after each IB schedule. Thus we should have same behavior without the hard lockup. Tested on R100,R200,R300,R400,R500,R600,R700 family. V2: Adjust fence counts in r600_blit_prepare_copy() Signed-off-by: Jerome Glisse <jglisse@redhat.com> Reviewed-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
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62cdc0c206
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cafe6609d6
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@ -356,6 +356,11 @@ void r100_fence_ring_emit(struct radeon_device *rdev,
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/* Wait until IDLE & CLEAN */
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radeon_ring_write(rdev, PACKET0(0x1720, 0));
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radeon_ring_write(rdev, (1 << 16) | (1 << 17));
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radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
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RADEON_HDP_READ_BUFFER_INVALIDATE);
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radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
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/* Emit fence sequence & fire IRQ */
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radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
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radeon_ring_write(rdev, fence->seq);
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@ -1713,14 +1718,6 @@ void r100_gpu_init(struct radeon_device *rdev)
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r100_hdp_reset(rdev);
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}
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void r100_hdp_flush(struct radeon_device *rdev)
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{
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u32 tmp;
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tmp = RREG32(RADEON_HOST_PATH_CNTL);
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tmp |= RADEON_HDP_READ_BUFFER_INVALIDATE;
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WREG32(RADEON_HOST_PATH_CNTL, tmp);
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}
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void r100_hdp_reset(struct radeon_device *rdev)
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{
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uint32_t tmp;
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@ -3313,6 +3310,7 @@ static int r100_startup(struct radeon_device *rdev)
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}
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/* Enable IRQ */
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r100_irq_set(rdev);
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rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -36,7 +36,15 @@
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#include "rv350d.h"
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#include "r300_reg_safe.h"
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/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
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/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
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*
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* GPU Errata:
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* - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
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* using MMIO to flush host path read cache, this lead to HARDLOCKUP.
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* However, scheduling such write to the ring seems harmless, i suspect
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* the CP read collide with the flush somehow, or maybe the MC, hard to
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* tell. (Jerome Glisse)
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*/
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/*
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* rv370,rv380 PCIE GART
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@ -178,6 +186,11 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
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/* Wait until IDLE & CLEAN */
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radeon_ring_write(rdev, PACKET0(0x1720, 0));
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radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
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radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
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RADEON_HDP_READ_BUFFER_INVALIDATE);
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radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
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radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
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/* Emit fence sequence & fire IRQ */
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radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
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radeon_ring_write(rdev, fence->seq);
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@ -1258,6 +1271,7 @@ static int r300_startup(struct radeon_device *rdev)
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}
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/* Enable IRQ */
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r100_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -219,6 +219,7 @@ static int r420_startup(struct radeon_device *rdev)
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r420_pipes_init(rdev);
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/* Enable IRQ */
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r100_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -186,6 +186,7 @@ static int r520_startup(struct radeon_device *rdev)
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}
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/* Enable IRQ */
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rs600_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -1388,11 +1388,6 @@ void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
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(void)RREG32(PCIE_PORT_DATA);
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}
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void r600_hdp_flush(struct radeon_device *rdev)
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{
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WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
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}
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/*
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* CP & Ring
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*/
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@ -1789,6 +1784,8 @@ void r600_fence_ring_emit(struct radeon_device *rdev,
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radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
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radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
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radeon_ring_write(rdev, fence->seq);
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radeon_ring_write(rdev, PACKET0(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0));
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radeon_ring_write(rdev, 1);
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/* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
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radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
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radeon_ring_write(rdev, RB_INT_STAT);
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@ -577,9 +577,9 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes)
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ring_size = num_loops * dwords_per_loop;
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/* set default + shaders */
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ring_size += 40; /* shaders + def state */
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ring_size += 5; /* fence emit for VB IB */
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ring_size += 7; /* fence emit for VB IB */
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ring_size += 5; /* done copy */
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ring_size += 5; /* fence emit for done copy */
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ring_size += 7; /* fence emit for done copy */
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r = radeon_ring_lock(rdev, ring_size);
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WARN_ON(r);
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@ -656,7 +656,6 @@ struct radeon_asic {
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uint32_t offset, uint32_t obj_size);
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int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
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void (*bandwidth_update)(struct radeon_device *rdev);
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void (*hdp_flush)(struct radeon_device *rdev);
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void (*hpd_init)(struct radeon_device *rdev);
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void (*hpd_fini)(struct radeon_device *rdev);
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bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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@ -669,12 +668,14 @@ struct radeon_asic {
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struct r100_asic {
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const unsigned *reg_safe_bm;
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unsigned reg_safe_bm_size;
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u32 hdp_cntl;
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};
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struct r300_asic {
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const unsigned *reg_safe_bm;
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unsigned reg_safe_bm_size;
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u32 resync_scratch;
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u32 hdp_cntl;
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};
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struct r600_asic {
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@ -1010,7 +1011,6 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
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#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
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#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
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#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
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#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
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#define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
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#define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
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#define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
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@ -77,7 +77,6 @@ int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
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void r100_bandwidth_update(struct radeon_device *rdev);
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void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
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int r100_ring_test(struct radeon_device *rdev);
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void r100_hdp_flush(struct radeon_device *rdev);
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void r100_hpd_init(struct radeon_device *rdev);
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void r100_hpd_fini(struct radeon_device *rdev);
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bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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@ -114,7 +113,6 @@ static struct radeon_asic r100_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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@ -174,7 +172,6 @@ static struct radeon_asic r300_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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@ -218,7 +215,6 @@ static struct radeon_asic r420_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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@ -267,7 +263,6 @@ static struct radeon_asic rs400_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &r100_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &r100_hpd_init,
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.hpd_fini = &r100_hpd_fini,
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.hpd_sense = &r100_hpd_sense,
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@ -324,7 +319,6 @@ static struct radeon_asic rs600_asic = {
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.set_pcie_lanes = NULL,
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.set_clock_gating = &radeon_atom_set_clock_gating,
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.bandwidth_update = &rs600_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &rs600_hpd_init,
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.hpd_fini = &rs600_hpd_fini,
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.hpd_sense = &rs600_hpd_sense,
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@ -372,7 +366,6 @@ static struct radeon_asic rs690_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &rs690_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &rs600_hpd_init,
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.hpd_fini = &rs600_hpd_fini,
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.hpd_sense = &rs600_hpd_sense,
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@ -424,7 +417,6 @@ static struct radeon_asic rv515_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &rv515_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &rs600_hpd_init,
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.hpd_fini = &rs600_hpd_fini,
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.hpd_sense = &rs600_hpd_sense,
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@ -467,7 +459,6 @@ static struct radeon_asic r520_asic = {
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.set_surface_reg = r100_set_surface_reg,
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.clear_surface_reg = r100_clear_surface_reg,
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.bandwidth_update = &rv515_bandwidth_update,
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.hdp_flush = &r100_hdp_flush,
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.hpd_init = &rs600_hpd_init,
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.hpd_fini = &rs600_hpd_fini,
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.hpd_sense = &rs600_hpd_sense,
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@ -508,7 +499,6 @@ int r600_ring_test(struct radeon_device *rdev);
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int r600_copy_blit(struct radeon_device *rdev,
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uint64_t src_offset, uint64_t dst_offset,
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unsigned num_pages, struct radeon_fence *fence);
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void r600_hdp_flush(struct radeon_device *rdev);
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void r600_hpd_init(struct radeon_device *rdev);
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void r600_hpd_fini(struct radeon_device *rdev);
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bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
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@ -544,7 +534,6 @@ static struct radeon_asic r600_asic = {
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.set_surface_reg = r600_set_surface_reg,
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.clear_surface_reg = r600_clear_surface_reg,
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.bandwidth_update = &rv515_bandwidth_update,
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.hdp_flush = &r600_hdp_flush,
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.hpd_init = &r600_hpd_init,
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.hpd_fini = &r600_hpd_fini,
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.hpd_sense = &r600_hpd_sense,
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@ -589,7 +578,6 @@ static struct radeon_asic rv770_asic = {
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.set_surface_reg = r600_set_surface_reg,
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.clear_surface_reg = r600_clear_surface_reg,
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.bandwidth_update = &rv515_bandwidth_update,
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.hdp_flush = &r600_hdp_flush,
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.hpd_init = &r600_hpd_init,
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.hpd_fini = &r600_hpd_fini,
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.hpd_sense = &r600_hpd_sense,
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printk(KERN_ERR "Failed to wait for object !\n");
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return r;
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}
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radeon_hdp_flush(robj->rdev);
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}
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return 0;
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}
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mutex_lock(&dev->struct_mutex);
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drm_gem_object_unreference(gobj);
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mutex_unlock(&dev->struct_mutex);
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radeon_hdp_flush(robj->rdev);
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return r;
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}
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@ -396,6 +396,7 @@ static int rs400_startup(struct radeon_device *rdev)
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return r;
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/* Enable IRQ */
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r100_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -554,6 +554,7 @@ static int rs600_startup(struct radeon_device *rdev)
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return r;
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/* Enable IRQ */
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rs600_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -626,6 +626,7 @@ static int rs690_startup(struct radeon_device *rdev)
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return r;
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/* Enable IRQ */
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rs600_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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@ -479,6 +479,7 @@ static int rv515_startup(struct radeon_device *rdev)
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}
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/* Enable IRQ */
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rs600_irq_set(rdev);
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rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
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/* 1M ring buffer */
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r = r100_cp_init(rdev, 1024 * 1024);
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if (r) {
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