Merge tag 'drm-intel-next-fixes-2018-03-27' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Display fixes for booting with MST hub lid closed and display freezing after hibernation (fd.o bugs 105470 & 105196) - Fix for a very rare interrupt handling race resulting in GPU hang * tag 'drm-intel-next-fixes-2018-03-27' of git://anongit.freedesktop.org/drm/drm-intel: drm/i915: Fix hibernation with ACPI S0 target state drm/i915/execlists: Use a locked clear_bit() for synchronisation with interrupt drm/i915: Specify which engines to reset following semaphore/event lockups drm/i915/dp: Write to SET_POWER dpcd to enable MST hub.
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commit
cb17aa521e
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@ -1611,15 +1611,12 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
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{
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struct drm_i915_private *dev_priv = to_i915(dev);
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struct pci_dev *pdev = dev_priv->drm.pdev;
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bool fw_csr;
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int ret;
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disable_rpm_wakeref_asserts(dev_priv);
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intel_display_set_init_power(dev_priv, false);
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fw_csr = !IS_GEN9_LP(dev_priv) && !hibernation &&
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suspend_to_idle(dev_priv) && dev_priv->csr.dmc_payload;
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/*
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* In case of firmware assisted context save/restore don't manually
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* deinit the power domains. This also means the CSR/DMC firmware will
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@ -1627,8 +1624,11 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
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* also enable deeper system power states that would be blocked if the
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* firmware was inactive.
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*/
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if (!fw_csr)
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if (IS_GEN9_LP(dev_priv) || hibernation || !suspend_to_idle(dev_priv) ||
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dev_priv->csr.dmc_payload == NULL) {
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intel_power_domains_suspend(dev_priv);
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dev_priv->power_domains_suspended = true;
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}
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ret = 0;
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if (IS_GEN9_LP(dev_priv))
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@ -1640,8 +1640,10 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
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if (ret) {
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DRM_ERROR("Suspend complete failed: %d\n", ret);
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if (!fw_csr)
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if (dev_priv->power_domains_suspended) {
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intel_power_domains_init_hw(dev_priv, true);
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dev_priv->power_domains_suspended = false;
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}
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goto out;
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}
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@ -1662,8 +1664,6 @@ static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
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if (!(hibernation && INTEL_GEN(dev_priv) < 6))
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pci_set_power_state(pdev, PCI_D3hot);
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dev_priv->suspended_to_idle = suspend_to_idle(dev_priv);
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out:
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enable_rpm_wakeref_asserts(dev_priv);
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@ -1830,8 +1830,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
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intel_uncore_resume_early(dev_priv);
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if (IS_GEN9_LP(dev_priv)) {
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if (!dev_priv->suspended_to_idle)
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gen9_sanitize_dc_state(dev_priv);
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gen9_sanitize_dc_state(dev_priv);
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bxt_disable_dc9(dev_priv);
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} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
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hsw_disable_pc8(dev_priv);
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@ -1839,8 +1838,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
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intel_uncore_sanitize(dev_priv);
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if (IS_GEN9_LP(dev_priv) ||
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!(dev_priv->suspended_to_idle && dev_priv->csr.dmc_payload))
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if (dev_priv->power_domains_suspended)
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intel_power_domains_init_hw(dev_priv, true);
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else
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intel_display_set_init_power(dev_priv, true);
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@ -1850,7 +1848,7 @@ static int i915_drm_resume_early(struct drm_device *dev)
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enable_rpm_wakeref_asserts(dev_priv);
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out:
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dev_priv->suspended_to_idle = false;
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dev_priv->power_domains_suspended = false;
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return ret;
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}
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@ -2119,7 +2119,7 @@ struct drm_i915_private {
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u32 bxt_phy_grc;
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u32 suspend_count;
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bool suspended_to_idle;
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bool power_domains_suspended;
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struct i915_suspend_saved_registers regfile;
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struct vlv_s0ix_state vlv_s0ix_state;
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@ -831,7 +831,8 @@ static void execlists_submission_tasklet(unsigned long data)
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struct drm_i915_private *dev_priv = engine->i915;
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bool fw = false;
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/* We can skip acquiring intel_runtime_pm_get() here as it was taken
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/*
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* We can skip acquiring intel_runtime_pm_get() here as it was taken
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* on our behalf by the request (see i915_gem_mark_busy()) and it will
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* not be relinquished until the device is idle (see
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* i915_gem_idle_work_handler()). As a precaution, we make sure
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@ -840,7 +841,8 @@ static void execlists_submission_tasklet(unsigned long data)
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*/
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GEM_BUG_ON(!dev_priv->gt.awake);
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/* Prefer doing test_and_clear_bit() as a two stage operation to avoid
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/*
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* Prefer doing test_and_clear_bit() as a two stage operation to avoid
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* imposing the cost of a locked atomic transaction when submitting a
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* new request (outside of the context-switch interrupt).
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*/
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@ -856,17 +858,10 @@ static void execlists_submission_tasklet(unsigned long data)
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execlists->csb_head = -1; /* force mmio read of CSB ptrs */
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}
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/* The write will be ordered by the uncached read (itself
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* a memory barrier), so we do not need another in the form
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* of a locked instruction. The race between the interrupt
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* handler and the split test/clear is harmless as we order
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* our clear before the CSB read. If the interrupt arrived
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* first between the test and the clear, we read the updated
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* CSB and clear the bit. If the interrupt arrives as we read
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* the CSB or later (i.e. after we had cleared the bit) the bit
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* is set and we do a new loop.
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*/
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__clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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/* Clear before reading to catch new interrupts */
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clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
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smp_mb__after_atomic();
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if (unlikely(execlists->csb_head == -1)) { /* following a reset */
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if (!fw) {
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intel_uncore_forcewake_get(dev_priv,
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