Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner: "Three patches addressing shortcomings in the ARM gic interrupt chip driver" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip: gic: Fix core ID calculation when topology is read from DT irqchip: gic: Add binding probe for ARM GIC400 irqchip: gic: Add support for cortex a7 compatible string
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commit
cb20fd0779
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@ -42,6 +42,7 @@
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqchip/arm-gic.h>
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#include <linux/irqchip/arm-gic.h>
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#include <asm/cputype.h>
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#include <asm/irq.h>
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#include <asm/irq.h>
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#include <asm/exception.h>
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#include <asm/exception.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_plat.h>
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@ -954,7 +955,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
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}
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}
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for_each_possible_cpu(cpu) {
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for_each_possible_cpu(cpu) {
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unsigned long offset = percpu_offset * cpu_logical_map(cpu);
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u32 mpidr = cpu_logical_map(cpu);
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u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
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unsigned long offset = percpu_offset * core_id;
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*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
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*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
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*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
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*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
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}
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}
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@ -1071,8 +1074,10 @@ gic_of_init(struct device_node *node, struct device_node *parent)
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gic_cnt++;
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gic_cnt++;
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return 0;
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return 0;
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}
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}
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IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
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IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
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IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
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IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
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IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
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IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
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IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
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IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
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IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
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IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
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