fpga: dfl: fme: add global error reporting support
This patch adds support for global error reporting for FPGA Management Engine (FME), it introduces sysfs interfaces to report different error detected by the hardware, and allow user to clear errors or inject error for testing purpose. Signed-off-by: Luwei Kang <luwei.kang@intel.com> Signed-off-by: Ananda Ravuri <ananda.ravuri@intel.com> Signed-off-by: Xu Yilun <yilun.xu@intel.com> Signed-off-by: Wu Hao <hao.wu@intel.com> Acked-by: Alan Tull <atull@kernel.org> Signed-off-by: Moritz Fischer <mdf@kernel.org>alistair/sunxi64-5.4-dsi
Wu Hao
Moritz Fischer
parent
bd127b8191
commit
cb3c2c47e3
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@ -44,3 +44,65 @@ Description: Read-only. It returns socket_id to indicate which socket
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this FPGA belongs to, only valid for integrated solution.
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User only needs this information, in case standard numa node
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can't provide correct information.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie0_errors
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Write. Read this file for errors detected on pcie0 link.
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Write this file to clear errors logged in pcie0_errors. Write
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fails with -EINVAL if input parsing fails or input error code
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doesn't match.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/pcie1_errors
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Write. Read this file for errors detected on pcie1 link.
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Write this file to clear errors logged in pcie1_errors. Write
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fails with -EINVAL if input parsing fails or input error code
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doesn't match.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/nonfatal_errors
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns non-fatal errors detected.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/catfatal_errors
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. It returns catastrophic and fatal errors detected.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/inject_errors
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Write. Read this file to check errors injected. Write this
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file to inject errors for testing purpose. Write fails with
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-EINVAL if input parsing fails or input inject error code isn't
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supported.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/fme_errors
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-Write. Read this file to get errors detected on FME.
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Write this file to clear errors logged in fme_errors. Write
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fials with -EINVAL if input parsing fails or input error code
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doesn't match.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/first_error
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. Read this file to get the first error detected by
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hardware.
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What: /sys/bus/platform/devices/dfl-fme.0/errors/next_error
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Date: August 2019
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KernelVersion: 5.4
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Contact: Wu Hao <hao.wu@intel.com>
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Description: Read-only. Read this file to get the second error detected by
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hardware.
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@ -39,7 +39,7 @@ obj-$(CONFIG_FPGA_DFL_FME_BRIDGE) += dfl-fme-br.o
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obj-$(CONFIG_FPGA_DFL_FME_REGION) += dfl-fme-region.o
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obj-$(CONFIG_FPGA_DFL_AFU) += dfl-afu.o
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dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o
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dfl-fme-objs := dfl-fme-main.o dfl-fme-pr.o dfl-fme-error.o
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dfl-afu-objs := dfl-afu-main.o dfl-afu-region.o dfl-afu-dma-region.o
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dfl-afu-objs += dfl-afu-error.o
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@ -0,0 +1,359 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for FPGA Management Engine Error Management
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*
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* Copyright 2019 Intel Corporation, Inc.
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*
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* Authors:
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* Kang Luwei <luwei.kang@intel.com>
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* Xiao Guangrong <guangrong.xiao@linux.intel.com>
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* Wu Hao <hao.wu@intel.com>
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* Joseph Grecco <joe.grecco@intel.com>
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* Enno Luebbers <enno.luebbers@intel.com>
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* Tim Whisonant <tim.whisonant@intel.com>
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* Ananda Ravuri <ananda.ravuri@intel.com>
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* Mitchel, Henry <henry.mitchel@intel.com>
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*/
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#include <linux/uaccess.h>
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#include "dfl.h"
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#include "dfl-fme.h"
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#define FME_ERROR_MASK 0x8
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#define FME_ERROR 0x10
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#define MBP_ERROR BIT_ULL(6)
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#define PCIE0_ERROR_MASK 0x18
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#define PCIE0_ERROR 0x20
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#define PCIE1_ERROR_MASK 0x28
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#define PCIE1_ERROR 0x30
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#define FME_FIRST_ERROR 0x38
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#define FME_NEXT_ERROR 0x40
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#define RAS_NONFAT_ERROR_MASK 0x48
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#define RAS_NONFAT_ERROR 0x50
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#define RAS_CATFAT_ERROR_MASK 0x58
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#define RAS_CATFAT_ERROR 0x60
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#define RAS_ERROR_INJECT 0x68
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#define INJECT_ERROR_MASK GENMASK_ULL(2, 0)
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#define ERROR_MASK GENMASK_ULL(63, 0)
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static ssize_t pcie0_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + PCIE0_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static ssize_t pcie0_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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int ret = 0;
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u64 v, val;
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if (kstrtou64(buf, 0, &val))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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writeq(GENMASK_ULL(63, 0), base + PCIE0_ERROR_MASK);
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v = readq(base + PCIE0_ERROR);
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if (val == v)
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writeq(v, base + PCIE0_ERROR);
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else
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ret = -EINVAL;
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writeq(0ULL, base + PCIE0_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(pcie0_errors);
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static ssize_t pcie1_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + PCIE1_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static ssize_t pcie1_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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int ret = 0;
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u64 v, val;
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if (kstrtou64(buf, 0, &val))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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writeq(GENMASK_ULL(63, 0), base + PCIE1_ERROR_MASK);
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v = readq(base + PCIE1_ERROR);
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if (val == v)
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writeq(v, base + PCIE1_ERROR);
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else
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ret = -EINVAL;
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writeq(0ULL, base + PCIE1_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(pcie1_errors);
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static ssize_t nonfatal_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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return sprintf(buf, "0x%llx\n",
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(unsigned long long)readq(base + RAS_NONFAT_ERROR));
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}
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static DEVICE_ATTR_RO(nonfatal_errors);
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static ssize_t catfatal_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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void __iomem *base;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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return sprintf(buf, "0x%llx\n",
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(unsigned long long)readq(base + RAS_CATFAT_ERROR));
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}
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static DEVICE_ATTR_RO(catfatal_errors);
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static ssize_t inject_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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v = readq(base + RAS_ERROR_INJECT);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n",
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(unsigned long long)FIELD_GET(INJECT_ERROR_MASK, v));
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}
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static ssize_t inject_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u8 inject_error;
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u64 v;
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if (kstrtou8(buf, 0, &inject_error))
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return -EINVAL;
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if (inject_error & ~INJECT_ERROR_MASK)
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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v = readq(base + RAS_ERROR_INJECT);
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v &= ~INJECT_ERROR_MASK;
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v |= FIELD_PREP(INJECT_ERROR_MASK, inject_error);
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writeq(v, base + RAS_ERROR_INJECT);
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mutex_unlock(&pdata->lock);
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return count;
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}
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static DEVICE_ATTR_RW(inject_errors);
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static ssize_t fme_errors_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + FME_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static ssize_t fme_errors_store(struct device *dev,
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struct device_attribute *attr,
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const char *buf, size_t count)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 v, val;
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int ret = 0;
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if (kstrtou64(buf, 0, &val))
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return -EINVAL;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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writeq(GENMASK_ULL(63, 0), base + FME_ERROR_MASK);
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v = readq(base + FME_ERROR);
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if (val == v)
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writeq(v, base + FME_ERROR);
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else
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ret = -EINVAL;
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/* Workaround: disable MBP_ERROR if feature revision is 0 */
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writeq(dfl_feature_revision(base) ? 0ULL : MBP_ERROR,
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base + FME_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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return ret ? ret : count;
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}
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static DEVICE_ATTR_RW(fme_errors);
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static ssize_t first_error_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + FME_FIRST_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static DEVICE_ATTR_RO(first_error);
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static ssize_t next_error_show(struct device *dev,
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struct device_attribute *attr, char *buf)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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u64 value;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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value = readq(base + FME_NEXT_ERROR);
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mutex_unlock(&pdata->lock);
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return sprintf(buf, "0x%llx\n", (unsigned long long)value);
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}
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static DEVICE_ATTR_RO(next_error);
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static struct attribute *fme_global_err_attrs[] = {
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&dev_attr_pcie0_errors.attr,
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&dev_attr_pcie1_errors.attr,
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&dev_attr_nonfatal_errors.attr,
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&dev_attr_catfatal_errors.attr,
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&dev_attr_inject_errors.attr,
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&dev_attr_fme_errors.attr,
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&dev_attr_first_error.attr,
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&dev_attr_next_error.attr,
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NULL,
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};
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static umode_t fme_global_err_attrs_visible(struct kobject *kobj,
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struct attribute *attr, int n)
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{
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struct device *dev = kobj_to_dev(kobj);
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/*
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* sysfs entries are visible only if related private feature is
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* enumerated.
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*/
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if (!dfl_get_feature_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR))
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return 0;
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return attr->mode;
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}
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const struct attribute_group fme_global_err_group = {
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.name = "errors",
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.attrs = fme_global_err_attrs,
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.is_visible = fme_global_err_attrs_visible,
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};
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static void fme_err_mask(struct device *dev, bool mask)
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{
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struct dfl_feature_platform_data *pdata = dev_get_platdata(dev);
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void __iomem *base;
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base = dfl_get_feature_ioaddr_by_id(dev, FME_FEATURE_ID_GLOBAL_ERR);
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mutex_lock(&pdata->lock);
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/* Workaround: keep MBP_ERROR always masked if revision is 0 */
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if (dfl_feature_revision(base))
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writeq(mask ? ERROR_MASK : 0, base + FME_ERROR_MASK);
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else
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writeq(mask ? ERROR_MASK : MBP_ERROR, base + FME_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + PCIE0_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + PCIE1_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + RAS_NONFAT_ERROR_MASK);
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writeq(mask ? ERROR_MASK : 0, base + RAS_CATFAT_ERROR_MASK);
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mutex_unlock(&pdata->lock);
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}
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static int fme_global_err_init(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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fme_err_mask(&pdev->dev, false);
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return 0;
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}
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static void fme_global_err_uinit(struct platform_device *pdev,
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struct dfl_feature *feature)
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{
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fme_err_mask(&pdev->dev, true);
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}
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const struct dfl_feature_id fme_global_err_id_table[] = {
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{.id = FME_FEATURE_ID_GLOBAL_ERR,},
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{0,}
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};
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const struct dfl_feature_ops fme_global_err_ops = {
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.init = fme_global_err_init,
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.uinit = fme_global_err_uinit,
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};
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@ -127,7 +127,10 @@ static struct attribute *fme_hdr_attrs[] = {
|
|||
&dev_attr_socket_id.attr,
|
||||
NULL,
|
||||
};
|
||||
ATTRIBUTE_GROUPS(fme_hdr);
|
||||
|
||||
static const struct attribute_group fme_hdr_group = {
|
||||
.attrs = fme_hdr_attrs,
|
||||
};
|
||||
|
||||
static long fme_hdr_ioctl_release_port(struct dfl_feature_platform_data *pdata,
|
||||
unsigned long arg)
|
||||
|
|
@ -187,6 +190,10 @@ static struct dfl_feature_driver fme_feature_drvs[] = {
|
|||
.id_table = fme_pr_mgmt_id_table,
|
||||
.ops = &fme_pr_mgmt_ops,
|
||||
},
|
||||
{
|
||||
.id_table = fme_global_err_id_table,
|
||||
.ops = &fme_global_err_ops,
|
||||
},
|
||||
{
|
||||
.ops = NULL,
|
||||
},
|
||||
|
|
@ -333,10 +340,16 @@ static int fme_remove(struct platform_device *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static const struct attribute_group *fme_dev_groups[] = {
|
||||
&fme_hdr_group,
|
||||
&fme_global_err_group,
|
||||
NULL
|
||||
};
|
||||
|
||||
static struct platform_driver fme_driver = {
|
||||
.driver = {
|
||||
.name = DFL_FPGA_FEATURE_DEV_FME,
|
||||
.dev_groups = fme_hdr_groups,
|
||||
.dev_groups = fme_dev_groups,
|
||||
},
|
||||
.probe = fme_probe,
|
||||
.remove = fme_remove,
|
||||
|
|
|
|||
|
|
@ -35,5 +35,8 @@ struct dfl_fme {
|
|||
|
||||
extern const struct dfl_feature_ops fme_pr_mgmt_ops;
|
||||
extern const struct dfl_feature_id fme_pr_mgmt_id_table[];
|
||||
extern const struct dfl_feature_ops fme_global_err_ops;
|
||||
extern const struct dfl_feature_id fme_global_err_id_table[];
|
||||
extern const struct attribute_group fme_global_err_group;
|
||||
|
||||
#endif /* __DFL_FME_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue