Merge branch 'x86/cpu' into x86/asm, to merge more patches
Signed-off-by: Ingo Molnar <mingo@kernel.org>
This commit is contained in:
commit
cb44d0cfc2
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@ -1,7 +1,6 @@
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#ifndef _ASM_IA64_IOMMU_H
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#define _ASM_IA64_IOMMU_H 1
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#define cpu_has_x2apic 0
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/* 10 seconds */
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#define DMAR_OPERATION_TIMEOUT (((cycles_t) local_cpu_data->itc_freq)*10)
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@ -97,8 +97,7 @@ static int __init early_init_dt_scan_serial(unsigned long node,
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return 0;
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#endif
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*addr64 = fdt_translate_address((const void *)initial_boot_params,
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node);
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*addr64 = of_flat_dt_translate_address(node);
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return *addr64 == OF_BAD_ADDR ? 0 : 1;
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}
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@ -562,7 +562,8 @@ static int __init camellia_aesni_init(void)
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{
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const char *feature_name;
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if (!cpu_has_avx2 || !cpu_has_avx || !cpu_has_aes || !cpu_has_osxsave) {
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if (!cpu_has_avx2 || !cpu_has_avx || !cpu_has_aes ||
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!boot_cpu_has(X86_FEATURE_OSXSAVE)) {
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pr_info("AVX2 or AES-NI instructions are not detected.\n");
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return -ENODEV;
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}
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@ -554,7 +554,7 @@ static int __init camellia_aesni_init(void)
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{
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const char *feature_name;
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if (!cpu_has_avx || !cpu_has_aes || !cpu_has_osxsave) {
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if (!cpu_has_avx || !cpu_has_aes || !boot_cpu_has(X86_FEATURE_OSXSAVE)) {
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pr_info("AVX or AES-NI instructions are not detected.\n");
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return -ENODEV;
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}
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@ -179,7 +179,7 @@ static struct shash_alg alg = {
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static int __init poly1305_simd_mod_init(void)
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{
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if (!cpu_has_xmm2)
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if (!boot_cpu_has(X86_FEATURE_XMM2))
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return -ENODEV;
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#ifdef CONFIG_AS_AVX2
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@ -538,7 +538,7 @@ static int __init init(void)
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{
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const char *feature_name;
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if (!cpu_has_avx2 || !cpu_has_osxsave) {
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if (!cpu_has_avx2 || !boot_cpu_has(X86_FEATURE_OSXSAVE)) {
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pr_info("AVX2 instructions are not detected.\n");
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return -ENODEV;
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}
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@ -600,7 +600,7 @@ static struct crypto_alg serpent_algs[10] = { {
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static int __init serpent_sse2_init(void)
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{
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if (!cpu_has_xmm2) {
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if (!boot_cpu_has(X86_FEATURE_XMM2)) {
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printk(KERN_INFO "SSE2 instructions are not detected.\n");
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return -ENODEV;
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}
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@ -677,7 +677,7 @@ static int __init cstate_pmu_init(void)
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{
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int err;
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if (cpu_has_hypervisor)
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if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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return -ENODEV;
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err = cstate_init();
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|
|
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@ -1383,7 +1383,7 @@ static int __init intel_uncore_init(void)
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if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
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return -ENODEV;
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if (cpu_has_hypervisor)
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if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
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return -ENODEV;
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max_packages = topology_max_packages();
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@ -239,10 +239,10 @@ extern void __init check_x2apic(void);
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extern void x2apic_setup(void);
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static inline int x2apic_enabled(void)
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{
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return cpu_has_x2apic && apic_is_x2apic_enabled();
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return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
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}
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#define x2apic_supported() (cpu_has_x2apic)
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#define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
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#else /* !CONFIG_X86_X2APIC */
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static inline void check_x2apic(void) { }
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static inline void x2apic_setup(void) { }
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|
|
@ -119,25 +119,16 @@ extern const char * const x86_bug_flags[NBUGINTS*32];
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} while (0)
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#define cpu_has_fpu boot_cpu_has(X86_FEATURE_FPU)
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#define cpu_has_pse boot_cpu_has(X86_FEATURE_PSE)
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#define cpu_has_tsc boot_cpu_has(X86_FEATURE_TSC)
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#define cpu_has_pge boot_cpu_has(X86_FEATURE_PGE)
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#define cpu_has_apic boot_cpu_has(X86_FEATURE_APIC)
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#define cpu_has_fxsr boot_cpu_has(X86_FEATURE_FXSR)
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#define cpu_has_xmm boot_cpu_has(X86_FEATURE_XMM)
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#define cpu_has_xmm2 boot_cpu_has(X86_FEATURE_XMM2)
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#define cpu_has_aes boot_cpu_has(X86_FEATURE_AES)
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#define cpu_has_avx boot_cpu_has(X86_FEATURE_AVX)
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#define cpu_has_avx2 boot_cpu_has(X86_FEATURE_AVX2)
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#define cpu_has_clflush boot_cpu_has(X86_FEATURE_CLFLUSH)
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#define cpu_has_gbpages boot_cpu_has(X86_FEATURE_GBPAGES)
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#define cpu_has_arch_perfmon boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
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#define cpu_has_pat boot_cpu_has(X86_FEATURE_PAT)
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#define cpu_has_x2apic boot_cpu_has(X86_FEATURE_X2APIC)
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#define cpu_has_xsave boot_cpu_has(X86_FEATURE_XSAVE)
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#define cpu_has_xsaves boot_cpu_has(X86_FEATURE_XSAVES)
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#define cpu_has_osxsave boot_cpu_has(X86_FEATURE_OSXSAVE)
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#define cpu_has_hypervisor boot_cpu_has(X86_FEATURE_HYPERVISOR)
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/*
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* Do not add any more of those clumsy macros - use static_cpu_has() for
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* fast paths and boot_cpu_has() otherwise!
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@ -183,7 +183,7 @@ static inline int pmd_trans_huge(pmd_t pmd)
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static inline int has_transparent_hugepage(void)
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{
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return cpu_has_pse;
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return boot_cpu_has(X86_FEATURE_PSE);
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}
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#ifdef __HAVE_ARCH_PTE_DEVMAP
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@ -181,7 +181,7 @@ static inline void __native_flush_tlb_single(unsigned long addr)
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static inline void __flush_tlb_all(void)
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{
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if (cpu_has_pge)
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if (static_cpu_has(X86_FEATURE_PGE))
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__flush_tlb_global();
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else
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__flush_tlb();
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@ -167,12 +167,12 @@ static struct xor_block_template xor_block_avx = {
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#define AVX_XOR_SPEED \
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do { \
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if (cpu_has_avx && cpu_has_osxsave) \
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if (cpu_has_avx && boot_cpu_has(X86_FEATURE_OSXSAVE)) \
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xor_speed(&xor_block_avx); \
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} while (0)
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#define AVX_SELECT(FASTEST) \
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(cpu_has_avx && cpu_has_osxsave ? &xor_block_avx : FASTEST)
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(cpu_has_avx && boot_cpu_has(X86_FEATURE_OSXSAVE) ? &xor_block_avx : FASTEST)
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#else
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@ -1561,7 +1561,7 @@ void __init check_x2apic(void)
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pr_info("x2apic: enabled by BIOS, switching to x2apic ops\n");
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x2apic_mode = 1;
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x2apic_state = X2APIC_ON;
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} else if (!cpu_has_x2apic) {
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} else if (!boot_cpu_has(X86_FEATURE_X2APIC)) {
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x2apic_state = X2APIC_DISABLED;
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}
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}
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@ -751,7 +751,7 @@ static void init_amd(struct cpuinfo_x86 *c)
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if (c->x86 >= 0xf)
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set_cpu_cap(c, X86_FEATURE_K8);
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if (cpu_has_xmm2) {
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if (cpu_has(c, X86_FEATURE_XMM2)) {
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/* MFENCE stops RDTSC speculation */
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set_cpu_cap(c, X86_FEATURE_MFENCE_RDTSC);
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}
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@ -152,9 +152,9 @@ static void early_init_intel(struct cpuinfo_x86 *c)
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* the TLB when any changes are made to any of the page table entries.
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* The operating system must reload CR3 to cause the TLB to be flushed"
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*
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* As a result cpu_has_pge() in arch/x86/include/asm/tlbflush.h should
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* be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
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* to be modified
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* As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
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* should be false so that __flush_tlb_all() causes CR3 insted of CR4.PGE
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* to be modified.
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*/
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if (c->x86 == 5 && c->x86_model == 9) {
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pr_info("Disabling PGE capability bit\n");
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@ -456,7 +456,7 @@ static void init_intel(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
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}
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if (cpu_has_xmm2)
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if (cpu_has(c, X86_FEATURE_XMM2))
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set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
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if (boot_cpu_has(X86_FEATURE_DS)) {
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@ -468,7 +468,7 @@ static void init_intel(struct cpuinfo_x86 *c)
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set_cpu_cap(c, X86_FEATURE_PEBS);
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}
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if (c->x86 == 6 && cpu_has_clflush &&
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if (c->x86 == 6 && boot_cpu_has(X86_FEATURE_CLFLUSH) &&
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(c->x86_model == 29 || c->x86_model == 46 || c->x86_model == 47))
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set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
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|
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|
@ -137,7 +137,7 @@ static void prepare_set(void)
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u32 cr0;
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
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if (cpu_has_pge) {
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if (boot_cpu_has(X86_FEATURE_PGE)) {
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cr4 = __read_cr4();
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__write_cr4(cr4 & ~X86_CR4_PGE);
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}
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|
@ -170,7 +170,7 @@ static void post_set(void)
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write_cr0(read_cr0() & ~X86_CR0_CD);
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/* Restore value of CR4 */
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if (cpu_has_pge)
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if (boot_cpu_has(X86_FEATURE_PGE))
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__write_cr4(cr4);
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}
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|
|
|
@ -741,7 +741,7 @@ static void prepare_set(void) __acquires(set_atomicity_lock)
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wbinvd();
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/* Save value of CR4 and clear Page Global Enable (bit 7) */
|
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if (cpu_has_pge) {
|
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if (boot_cpu_has(X86_FEATURE_PGE)) {
|
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cr4 = __read_cr4();
|
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__write_cr4(cr4 & ~X86_CR4_PGE);
|
||||
}
|
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|
@ -771,7 +771,7 @@ static void post_set(void) __releases(set_atomicity_lock)
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|||
write_cr0(read_cr0() & ~X86_CR0_CD);
|
||||
|
||||
/* Restore value of CR4 */
|
||||
if (cpu_has_pge)
|
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if (boot_cpu_has(X86_FEATURE_PGE))
|
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__write_cr4(cr4);
|
||||
raw_spin_unlock(&set_atomicity_lock);
|
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}
|
||||
|
|
|
@ -94,7 +94,7 @@ static void __init vmware_platform_setup(void)
|
|||
*/
|
||||
static uint32_t __init vmware_platform(void)
|
||||
{
|
||||
if (cpu_has_hypervisor) {
|
||||
if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
|
||||
unsigned int eax;
|
||||
unsigned int hyper_vendor_id[3];
|
||||
|
||||
|
|
|
@ -522,7 +522,7 @@ static noinline uint32_t __kvm_cpuid_base(void)
|
|||
if (boot_cpu_data.cpuid_level < 0)
|
||||
return 0; /* So we don't blow up on old processors */
|
||||
|
||||
if (cpu_has_hypervisor)
|
||||
if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
|
||||
return hypervisor_cpuid_base("KVMKVMKVM\0\0\0", 0);
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -40,7 +40,7 @@
|
|||
static inline void flush_tce(void* tceaddr)
|
||||
{
|
||||
/* a single tce can't cross a cache line */
|
||||
if (cpu_has_clflush)
|
||||
if (boot_cpu_has(X86_FEATURE_CLFLUSH))
|
||||
clflush(tceaddr);
|
||||
else
|
||||
wbinvd();
|
||||
|
|
|
@ -3836,7 +3836,8 @@ reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
|
|||
__reset_rsvds_bits_mask(vcpu, &context->shadow_zero_check,
|
||||
boot_cpu_data.x86_phys_bits,
|
||||
context->shadow_root_level, false,
|
||||
cpu_has_gbpages, true, true);
|
||||
boot_cpu_has(X86_FEATURE_GBPAGES),
|
||||
true, true);
|
||||
else
|
||||
__reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
|
||||
boot_cpu_data.x86_phys_bits,
|
||||
|
|
|
@ -612,7 +612,7 @@ unsigned long __copy_from_user_ll_nocache(void *to, const void __user *from,
|
|||
{
|
||||
stac();
|
||||
#ifdef CONFIG_X86_INTEL_USERCOPY
|
||||
if (n > 64 && cpu_has_xmm2)
|
||||
if (n > 64 && static_cpu_has(X86_FEATURE_XMM2))
|
||||
n = __copy_user_zeroing_intel_nocache(to, from, n);
|
||||
else
|
||||
__copy_user_zeroing(to, from, n);
|
||||
|
@ -629,7 +629,7 @@ unsigned long __copy_from_user_ll_nocache_nozero(void *to, const void __user *fr
|
|||
{
|
||||
stac();
|
||||
#ifdef CONFIG_X86_INTEL_USERCOPY
|
||||
if (n > 64 && cpu_has_xmm2)
|
||||
if (n > 64 && static_cpu_has(X86_FEATURE_XMM2))
|
||||
n = __copy_user_intel_nocache(to, from, n);
|
||||
else
|
||||
__copy_user(to, from, n);
|
||||
|
|
|
@ -162,7 +162,7 @@ static __init int setup_hugepagesz(char *opt)
|
|||
unsigned long ps = memparse(opt, &opt);
|
||||
if (ps == PMD_SIZE) {
|
||||
hugetlb_add_hstate(PMD_SHIFT - PAGE_SHIFT);
|
||||
} else if (ps == PUD_SIZE && cpu_has_gbpages) {
|
||||
} else if (ps == PUD_SIZE && boot_cpu_has(X86_FEATURE_GBPAGES)) {
|
||||
hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT);
|
||||
} else {
|
||||
printk(KERN_ERR "hugepagesz: Unsupported page size %lu M\n",
|
||||
|
@ -177,7 +177,7 @@ __setup("hugepagesz=", setup_hugepagesz);
|
|||
static __init int gigantic_pages_init(void)
|
||||
{
|
||||
/* With compaction or CMA we can allocate gigantic pages at runtime */
|
||||
if (cpu_has_gbpages && !size_to_hstate(1UL << PUD_SHIFT))
|
||||
if (boot_cpu_has(X86_FEATURE_GBPAGES) && !size_to_hstate(1UL << PUD_SHIFT))
|
||||
hugetlb_add_hstate(PUD_SHIFT - PAGE_SHIFT);
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -157,23 +157,23 @@ static void __init probe_page_size_mask(void)
|
|||
* This will simplify cpa(), which otherwise needs to support splitting
|
||||
* large pages into small in interrupt context, etc.
|
||||
*/
|
||||
if (cpu_has_pse && !debug_pagealloc_enabled())
|
||||
if (boot_cpu_has(X86_FEATURE_PSE) && !debug_pagealloc_enabled())
|
||||
page_size_mask |= 1 << PG_LEVEL_2M;
|
||||
#endif
|
||||
|
||||
/* Enable PSE if available */
|
||||
if (cpu_has_pse)
|
||||
if (boot_cpu_has(X86_FEATURE_PSE))
|
||||
cr4_set_bits_and_update_boot(X86_CR4_PSE);
|
||||
|
||||
/* Enable PGE if available */
|
||||
if (cpu_has_pge) {
|
||||
if (boot_cpu_has(X86_FEATURE_PGE)) {
|
||||
cr4_set_bits_and_update_boot(X86_CR4_PGE);
|
||||
__supported_pte_mask |= _PAGE_GLOBAL;
|
||||
} else
|
||||
__supported_pte_mask &= ~_PAGE_GLOBAL;
|
||||
|
||||
/* Enable 1 GB linear kernel mappings if available: */
|
||||
if (direct_gbpages && cpu_has_gbpages) {
|
||||
if (direct_gbpages && boot_cpu_has(X86_FEATURE_GBPAGES)) {
|
||||
printk(KERN_INFO "Using GB pages for direct mapping\n");
|
||||
page_size_mask |= 1 << PG_LEVEL_1G;
|
||||
} else {
|
||||
|
|
|
@ -284,7 +284,7 @@ kernel_physical_mapping_init(unsigned long start,
|
|||
*/
|
||||
mapping_iter = 1;
|
||||
|
||||
if (!cpu_has_pse)
|
||||
if (!boot_cpu_has(X86_FEATURE_PSE))
|
||||
use_pse = 0;
|
||||
|
||||
repeat:
|
||||
|
|
|
@ -1295,7 +1295,7 @@ int __meminit vmemmap_populate(unsigned long start, unsigned long end, int node)
|
|||
struct vmem_altmap *altmap = to_vmem_altmap(start);
|
||||
int err;
|
||||
|
||||
if (cpu_has_pse)
|
||||
if (boot_cpu_has(X86_FEATURE_PSE))
|
||||
err = vmemmap_populate_hugepages(start, end, node, altmap);
|
||||
else if (altmap) {
|
||||
pr_err_once("%s: no cpu support for altmap allocations\n",
|
||||
|
@ -1338,7 +1338,7 @@ void register_page_bootmem_memmap(unsigned long section_nr,
|
|||
}
|
||||
get_page_bootmem(section_nr, pud_page(*pud), MIX_SECTION_INFO);
|
||||
|
||||
if (!cpu_has_pse) {
|
||||
if (!boot_cpu_has(X86_FEATURE_PSE)) {
|
||||
next = (addr + PAGE_SIZE) & PAGE_MASK;
|
||||
pmd = pmd_offset(pud, addr);
|
||||
if (pmd_none(*pmd))
|
||||
|
|
|
@ -378,7 +378,7 @@ EXPORT_SYMBOL(iounmap);
|
|||
int __init arch_ioremap_pud_supported(void)
|
||||
{
|
||||
#ifdef CONFIG_X86_64
|
||||
return cpu_has_gbpages;
|
||||
return boot_cpu_has(X86_FEATURE_GBPAGES);
|
||||
#else
|
||||
return 0;
|
||||
#endif
|
||||
|
@ -386,7 +386,7 @@ int __init arch_ioremap_pud_supported(void)
|
|||
|
||||
int __init arch_ioremap_pmd_supported(void)
|
||||
{
|
||||
return cpu_has_pse;
|
||||
return boot_cpu_has(X86_FEATURE_PSE);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
|
@ -1055,7 +1055,7 @@ static int populate_pud(struct cpa_data *cpa, unsigned long start, pgd_t *pgd,
|
|||
/*
|
||||
* Map everything starting from the Gb boundary, possibly with 1G pages
|
||||
*/
|
||||
while (cpu_has_gbpages && end - start >= PUD_SIZE) {
|
||||
while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) {
|
||||
set_pud(pud, __pud(cpa->pfn << PAGE_SHIFT | _PAGE_PSE |
|
||||
massage_pgprot(pud_pgprot)));
|
||||
|
||||
|
@ -1460,7 +1460,7 @@ static int change_page_attr_set_clr(unsigned long *addr, int numpages,
|
|||
* error case we fall back to cpa_flush_all (which uses
|
||||
* WBINVD):
|
||||
*/
|
||||
if (!ret && cpu_has_clflush) {
|
||||
if (!ret && boot_cpu_has(X86_FEATURE_CLFLUSH)) {
|
||||
if (cpa.flags & (CPA_PAGES_ARRAY | CPA_ARRAY)) {
|
||||
cpa_flush_array(addr, numpages, cache,
|
||||
cpa.flags, pages);
|
||||
|
|
|
@ -636,7 +636,7 @@ static int __init ppro_init(char **cpu_type)
|
|||
__u8 cpu_model = boot_cpu_data.x86_model;
|
||||
struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
|
||||
|
||||
if (force_cpu_type == arch_perfmon && cpu_has_arch_perfmon)
|
||||
if (force_cpu_type == arch_perfmon && boot_cpu_has(X86_FEATURE_ARCH_PERFMON))
|
||||
return 0;
|
||||
|
||||
/*
|
||||
|
@ -761,7 +761,7 @@ int __init op_nmi_init(struct oprofile_operations *ops)
|
|||
if (cpu_type)
|
||||
break;
|
||||
|
||||
if (!cpu_has_arch_perfmon)
|
||||
if (!boot_cpu_has(X86_FEATURE_ARCH_PERFMON))
|
||||
return -ENODEV;
|
||||
|
||||
/* use arch perfmon as fallback */
|
||||
|
|
|
@ -75,7 +75,7 @@ static void ppro_setup_ctrs(struct op_x86_model_spec const *model,
|
|||
u64 val;
|
||||
int i;
|
||||
|
||||
if (cpu_has_arch_perfmon) {
|
||||
if (boot_cpu_has(X86_FEATURE_ARCH_PERFMON)) {
|
||||
union cpuid10_eax eax;
|
||||
eax.full = cpuid_eax(0xa);
|
||||
|
||||
|
|
|
@ -106,7 +106,7 @@ static int resume_physical_mapping_init(pgd_t *pgd_base)
|
|||
* normal page tables.
|
||||
* NOTE: We can mark everything as executable here
|
||||
*/
|
||||
if (cpu_has_pse) {
|
||||
if (boot_cpu_has(X86_FEATURE_PSE)) {
|
||||
set_pmd(pmd, pfn_pmd(pfn, PAGE_KERNEL_LARGE_EXEC));
|
||||
pfn += PTRS_PER_PTE;
|
||||
} else {
|
||||
|
|
|
@ -1469,10 +1469,10 @@ static void xen_pvh_set_cr_flags(int cpu)
|
|||
* For BSP, PSE PGE are set in probe_page_size_mask(), for APs
|
||||
* set them here. For all, OSFXSR OSXMMEXCPT are set in fpu__init_cpu().
|
||||
*/
|
||||
if (cpu_has_pse)
|
||||
if (boot_cpu_has(X86_FEATURE_PSE))
|
||||
cr4_set_bits_and_update_boot(X86_CR4_PSE);
|
||||
|
||||
if (cpu_has_pge)
|
||||
if (boot_cpu_has(X86_FEATURE_PGE))
|
||||
cr4_set_bits_and_update_boot(X86_CR4_PGE);
|
||||
}
|
||||
|
||||
|
|
|
@ -178,6 +178,8 @@ int pkcs7_validate_trust(struct pkcs7_message *pkcs7,
|
|||
int cached_ret = -ENOKEY;
|
||||
int ret;
|
||||
|
||||
*_trusted = false;
|
||||
|
||||
for (p = pkcs7->certs; p; p = p->next)
|
||||
p->seen = false;
|
||||
|
||||
|
|
|
@ -72,7 +72,7 @@ drm_clflush_pages(struct page *pages[], unsigned long num_pages)
|
|||
{
|
||||
|
||||
#if defined(CONFIG_X86)
|
||||
if (cpu_has_clflush) {
|
||||
if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
|
||||
drm_cache_flush_clflush(pages, num_pages);
|
||||
return;
|
||||
}
|
||||
|
@ -105,7 +105,7 @@ void
|
|||
drm_clflush_sg(struct sg_table *st)
|
||||
{
|
||||
#if defined(CONFIG_X86)
|
||||
if (cpu_has_clflush) {
|
||||
if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
|
||||
struct sg_page_iter sg_iter;
|
||||
|
||||
mb();
|
||||
|
@ -129,7 +129,7 @@ void
|
|||
drm_clflush_virt_range(void *addr, unsigned long length)
|
||||
{
|
||||
#if defined(CONFIG_X86)
|
||||
if (cpu_has_clflush) {
|
||||
if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
|
||||
const int size = boot_cpu_data.x86_clflush_size;
|
||||
void *end = addr + length;
|
||||
addr = (void *)(((unsigned long)addr) & -size);
|
||||
|
|
|
@ -488,7 +488,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
|
|||
ret = relocate_entry_cpu(obj, reloc, target_offset);
|
||||
else if (obj->map_and_fenceable)
|
||||
ret = relocate_entry_gtt(obj, reloc, target_offset);
|
||||
else if (cpu_has_clflush)
|
||||
else if (static_cpu_has(X86_FEATURE_CLFLUSH))
|
||||
ret = relocate_entry_clflush(obj, reloc, target_offset);
|
||||
else {
|
||||
WARN_ONCE(1, "Impossible case in relocation handling\n");
|
||||
|
|
|
@ -85,6 +85,9 @@ static struct max1111_data *the_max1111;
|
|||
|
||||
int max1111_read_channel(int channel)
|
||||
{
|
||||
if (!the_max1111 || !the_max1111->spi)
|
||||
return -ENODEV;
|
||||
|
||||
return max1111_read(&the_max1111->spi->dev, channel);
|
||||
}
|
||||
EXPORT_SYMBOL(max1111_read_channel);
|
||||
|
@ -258,6 +261,9 @@ static int max1111_remove(struct spi_device *spi)
|
|||
{
|
||||
struct max1111_data *data = spi_get_drvdata(spi);
|
||||
|
||||
#ifdef CONFIG_SHARPSL_PM
|
||||
the_max1111 = NULL;
|
||||
#endif
|
||||
hwmon_device_unregister(data->hwmon_dev);
|
||||
sysfs_remove_group(&spi->dev.kobj, &max1110_attr_group);
|
||||
sysfs_remove_group(&spi->dev.kobj, &max1111_attr_group);
|
||||
|
|
|
@ -599,7 +599,7 @@ void __init lguest_arch_host_init(void)
|
|||
* doing this.
|
||||
*/
|
||||
get_online_cpus();
|
||||
if (cpu_has_pge) { /* We have a broader idea of "global". */
|
||||
if (boot_cpu_has(X86_FEATURE_PGE)) { /* We have a broader idea of "global". */
|
||||
/* Remember that this was originally set (for cleanup). */
|
||||
cpu_had_pge = 1;
|
||||
/*
|
||||
|
|
|
@ -2425,7 +2425,7 @@ static __init uint32_t visorutil_spar_detect(void)
|
|||
{
|
||||
unsigned int eax, ebx, ecx, edx;
|
||||
|
||||
if (cpu_has_hypervisor) {
|
||||
if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
|
||||
/* check the ID */
|
||||
cpuid(UNISYS_SPAR_LEAF_ID, &eax, &ebx, &ecx, &edx);
|
||||
return (ebx == UNISYS_SPAR_ID_EBX) &&
|
||||
|
|
|
@ -343,13 +343,12 @@ static struct config_group *make_cluster(struct config_group *g,
|
|||
struct dlm_cluster *cl = NULL;
|
||||
struct dlm_spaces *sps = NULL;
|
||||
struct dlm_comms *cms = NULL;
|
||||
void *gps = NULL;
|
||||
|
||||
cl = kzalloc(sizeof(struct dlm_cluster), GFP_NOFS);
|
||||
sps = kzalloc(sizeof(struct dlm_spaces), GFP_NOFS);
|
||||
cms = kzalloc(sizeof(struct dlm_comms), GFP_NOFS);
|
||||
|
||||
if (!cl || !gps || !sps || !cms)
|
||||
if (!cl || !sps || !cms)
|
||||
goto fail;
|
||||
|
||||
config_group_init_type_name(&cl->group, name, &cluster_type);
|
||||
|
|
Loading…
Reference in a new issue