drm/radeon: update CIK soft reset
Update to the newer programming model. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>hifive-unleashed-5.1
Alex Deucher
parent
44fa346f7a
commit
cc066715e6
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@ -72,9 +72,11 @@ extern int r600_ih_ring_alloc(struct radeon_device *rdev);
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extern void r600_ih_ring_fini(struct radeon_device *rdev);
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extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
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extern bool evergreen_is_display_hung(struct radeon_device *rdev);
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extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
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extern void si_rlc_fini(struct radeon_device *rdev);
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extern int si_rlc_init(struct radeon_device *rdev);
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static void cik_rlc_stop(struct radeon_device *rdev);
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#define BONAIRE_IO_MC_REGS_SIZE 36
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@ -2733,8 +2735,269 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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return r;
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}
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static void cik_print_gpu_status_regs(struct radeon_device *rdev)
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{
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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dev_info(rdev->dev, " SDMA0_STATUS_REG = 0x%08X\n",
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RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET));
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dev_info(rdev->dev, " SDMA1_STATUS_REG = 0x%08X\n",
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RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET));
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}
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/**
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* cik_gpu_is_lockup - check if the 3D engine is locked up
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* cik_gpu_check_soft_reset - check which blocks are busy
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*
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* @rdev: radeon_device pointer
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*
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* Check which blocks are busy and return the relevant reset
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* mask to be used by cik_gpu_soft_reset().
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* Returns a mask of the blocks to be reset.
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*/
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static u32 cik_gpu_check_soft_reset(struct radeon_device *rdev)
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{
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u32 reset_mask = 0;
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u32 tmp;
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/* GRBM_STATUS */
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tmp = RREG32(GRBM_STATUS);
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if (tmp & (PA_BUSY | SC_BUSY |
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BCI_BUSY | SX_BUSY |
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TA_BUSY | VGT_BUSY |
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DB_BUSY | CB_BUSY |
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GDS_BUSY | SPI_BUSY |
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IA_BUSY | IA_BUSY_NO_DMA))
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reset_mask |= RADEON_RESET_GFX;
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if (tmp & (CP_BUSY | CP_COHERENCY_BUSY))
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reset_mask |= RADEON_RESET_CP;
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/* GRBM_STATUS2 */
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tmp = RREG32(GRBM_STATUS2);
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if (tmp & RLC_BUSY)
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reset_mask |= RADEON_RESET_RLC;
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/* SDMA0_STATUS_REG */
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tmp = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
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if (!(tmp & SDMA_IDLE))
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reset_mask |= RADEON_RESET_DMA;
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/* SDMA1_STATUS_REG */
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tmp = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
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if (!(tmp & SDMA_IDLE))
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reset_mask |= RADEON_RESET_DMA1;
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/* SRBM_STATUS2 */
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tmp = RREG32(SRBM_STATUS2);
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if (tmp & SDMA_BUSY)
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reset_mask |= RADEON_RESET_DMA;
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if (tmp & SDMA1_BUSY)
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reset_mask |= RADEON_RESET_DMA1;
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/* SRBM_STATUS */
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tmp = RREG32(SRBM_STATUS);
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if (tmp & IH_BUSY)
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reset_mask |= RADEON_RESET_IH;
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if (tmp & SEM_BUSY)
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reset_mask |= RADEON_RESET_SEM;
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if (tmp & GRBM_RQ_PENDING)
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reset_mask |= RADEON_RESET_GRBM;
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if (tmp & VMC_BUSY)
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reset_mask |= RADEON_RESET_VMC;
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if (tmp & (MCB_BUSY | MCB_NON_DISPLAY_BUSY |
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MCC_BUSY | MCD_BUSY))
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reset_mask |= RADEON_RESET_MC;
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if (evergreen_is_display_hung(rdev))
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reset_mask |= RADEON_RESET_DISPLAY;
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/* Skip MC reset as it's mostly likely not hung, just busy */
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if (reset_mask & RADEON_RESET_MC) {
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DRM_DEBUG("MC busy: 0x%08X, clearing.\n", reset_mask);
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reset_mask &= ~RADEON_RESET_MC;
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}
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return reset_mask;
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}
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/**
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* cik_gpu_soft_reset - soft reset GPU
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*
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* @rdev: radeon_device pointer
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* @reset_mask: mask of which blocks to reset
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*
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* Soft reset the blocks specified in @reset_mask.
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*/
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static void cik_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
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{
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struct evergreen_mc_save save;
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u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
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u32 tmp;
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if (reset_mask == 0)
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return;
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dev_info(rdev->dev, "GPU softreset: 0x%08X\n", reset_mask);
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cik_print_gpu_status_regs(rdev);
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x%08X\n",
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RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
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dev_info(rdev->dev, " VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
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RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
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/* stop the rlc */
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cik_rlc_stop(rdev);
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/* Disable GFX parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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/* Disable MEC parsing/prefetching */
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WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
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if (reset_mask & RADEON_RESET_DMA) {
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/* sdma0 */
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tmp = RREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET);
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tmp |= SDMA_HALT;
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WREG32(SDMA0_ME_CNTL + SDMA0_REGISTER_OFFSET, tmp);
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}
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if (reset_mask & RADEON_RESET_DMA1) {
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/* sdma1 */
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tmp = RREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET);
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tmp |= SDMA_HALT;
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WREG32(SDMA0_ME_CNTL + SDMA1_REGISTER_OFFSET, tmp);
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}
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evergreen_mc_stop(rdev, &save);
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if (evergreen_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP))
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grbm_soft_reset = SOFT_RESET_CP | SOFT_RESET_GFX;
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if (reset_mask & RADEON_RESET_CP) {
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grbm_soft_reset |= SOFT_RESET_CP;
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srbm_soft_reset |= SOFT_RESET_GRBM;
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}
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if (reset_mask & RADEON_RESET_DMA)
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srbm_soft_reset |= SOFT_RESET_SDMA;
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if (reset_mask & RADEON_RESET_DMA1)
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srbm_soft_reset |= SOFT_RESET_SDMA1;
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if (reset_mask & RADEON_RESET_DISPLAY)
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srbm_soft_reset |= SOFT_RESET_DC;
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if (reset_mask & RADEON_RESET_RLC)
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grbm_soft_reset |= SOFT_RESET_RLC;
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if (reset_mask & RADEON_RESET_SEM)
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srbm_soft_reset |= SOFT_RESET_SEM;
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if (reset_mask & RADEON_RESET_IH)
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srbm_soft_reset |= SOFT_RESET_IH;
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if (reset_mask & RADEON_RESET_GRBM)
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srbm_soft_reset |= SOFT_RESET_GRBM;
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if (reset_mask & RADEON_RESET_VMC)
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srbm_soft_reset |= SOFT_RESET_VMC;
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if (!(rdev->flags & RADEON_IS_IGP)) {
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if (reset_mask & RADEON_RESET_MC)
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srbm_soft_reset |= SOFT_RESET_MC;
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}
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if (grbm_soft_reset) {
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tmp = RREG32(GRBM_SOFT_RESET);
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tmp |= grbm_soft_reset;
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dev_info(rdev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(GRBM_SOFT_RESET, tmp);
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tmp = RREG32(GRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~grbm_soft_reset;
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WREG32(GRBM_SOFT_RESET, tmp);
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tmp = RREG32(GRBM_SOFT_RESET);
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}
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if (srbm_soft_reset) {
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tmp = RREG32(SRBM_SOFT_RESET);
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tmp |= srbm_soft_reset;
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dev_info(rdev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
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WREG32(SRBM_SOFT_RESET, tmp);
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tmp = RREG32(SRBM_SOFT_RESET);
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udelay(50);
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tmp &= ~srbm_soft_reset;
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WREG32(SRBM_SOFT_RESET, tmp);
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tmp = RREG32(SRBM_SOFT_RESET);
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}
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/* Wait a little for things to settle down */
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udelay(50);
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evergreen_mc_resume(rdev, &save);
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udelay(50);
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cik_print_gpu_status_regs(rdev);
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}
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/**
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* cik_asic_reset - soft reset GPU
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*
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* @rdev: radeon_device pointer
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*
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* Look up which blocks are hung and attempt
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* to reset them.
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* Returns 0 for success.
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*/
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int cik_asic_reset(struct radeon_device *rdev)
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{
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u32 reset_mask;
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reset_mask = cik_gpu_check_soft_reset(rdev);
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if (reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, true);
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cik_gpu_soft_reset(rdev, reset_mask);
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reset_mask = cik_gpu_check_soft_reset(rdev);
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if (!reset_mask)
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r600_set_bios_scratch_engine_hung(rdev, false);
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return 0;
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}
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/**
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* cik_gfx_is_lockup - check if the 3D engine is locked up
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*
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* @rdev: radeon_device pointer
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* @ring: radeon_ring structure holding ring information
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@ -2742,21 +3005,13 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
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* Check if the 3D engine is locked up (CIK).
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* Returns true if the engine is locked, false if not.
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*/
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bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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bool cik_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 srbm_status, srbm_status2;
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u32 grbm_status, grbm_status2;
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u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3;
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u32 reset_mask = cik_gpu_check_soft_reset(rdev);
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srbm_status = RREG32(SRBM_STATUS);
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srbm_status2 = RREG32(SRBM_STATUS2);
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grbm_status = RREG32(GRBM_STATUS);
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grbm_status2 = RREG32(GRBM_STATUS2);
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grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
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grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
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grbm_status_se2 = RREG32(GRBM_STATUS_SE2);
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grbm_status_se3 = RREG32(GRBM_STATUS_SE3);
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if (!(grbm_status & GUI_ACTIVE)) {
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if (!(reset_mask & (RADEON_RESET_GFX |
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RADEON_RESET_COMPUTE |
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RADEON_RESET_CP))) {
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radeon_ring_lockup_update(ring);
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return false;
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}
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@ -2765,168 +3020,6 @@ bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
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return radeon_ring_test_lockup(rdev, ring);
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}
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/**
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* cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG
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*
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* @rdev: radeon_device pointer
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*
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* Soft reset the GFX engine and CPG blocks (CIK).
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* XXX: deal with reseting RLC and CPF
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* Returns 0 for success.
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*/
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static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
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return 0;
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dev_info(rdev->dev, "GPU GFX softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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evergreen_mc_stop(rdev, &save);
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if (radeon_mc_wait_for_idle(rdev)) {
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dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
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}
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/* Disable CP parsing/prefetching */
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WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
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/* reset all the gfx block and all CPG blocks */
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grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX;
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dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
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WREG32(GRBM_SOFT_RESET, grbm_reset);
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(void)RREG32(GRBM_SOFT_RESET);
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udelay(50);
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WREG32(GRBM_SOFT_RESET, 0);
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(void)RREG32(GRBM_SOFT_RESET);
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/* Wait a little for things to settle down */
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udelay(50);
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
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dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
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RREG32(GRBM_STATUS_SE1));
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dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
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RREG32(GRBM_STATUS_SE2));
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dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
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RREG32(GRBM_STATUS_SE3));
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dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
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RREG32(SRBM_STATUS));
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dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
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RREG32(SRBM_STATUS2));
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evergreen_mc_resume(rdev, &save);
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return 0;
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}
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/**
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* cik_compute_gpu_soft_reset - soft reset CPC
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*
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* @rdev: radeon_device pointer
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*
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* Soft reset the CPC blocks (CIK).
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* XXX: deal with reseting RLC and CPF
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* Returns 0 for success.
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*/
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static int cik_compute_gpu_soft_reset(struct radeon_device *rdev)
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{
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struct evergreen_mc_save save;
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u32 grbm_reset = 0;
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dev_info(rdev->dev, "GPU compute softreset \n");
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dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
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RREG32(GRBM_STATUS));
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dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
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RREG32(GRBM_STATUS2));
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dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
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RREG32(GRBM_STATUS_SE0));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE1));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE2));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE3));
|
||||
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
||||
RREG32(SRBM_STATUS));
|
||||
dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
|
||||
RREG32(SRBM_STATUS2));
|
||||
evergreen_mc_stop(rdev, &save);
|
||||
if (radeon_mc_wait_for_idle(rdev)) {
|
||||
dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
|
||||
}
|
||||
/* Disable CP parsing/prefetching */
|
||||
WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
|
||||
|
||||
/* reset all the CPC blocks */
|
||||
grbm_reset = SOFT_RESET_CPG;
|
||||
|
||||
dev_info(rdev->dev, " GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
|
||||
WREG32(GRBM_SOFT_RESET, grbm_reset);
|
||||
(void)RREG32(GRBM_SOFT_RESET);
|
||||
udelay(50);
|
||||
WREG32(GRBM_SOFT_RESET, 0);
|
||||
(void)RREG32(GRBM_SOFT_RESET);
|
||||
/* Wait a little for things to settle down */
|
||||
udelay(50);
|
||||
dev_info(rdev->dev, " GRBM_STATUS=0x%08X\n",
|
||||
RREG32(GRBM_STATUS));
|
||||
dev_info(rdev->dev, " GRBM_STATUS2=0x%08X\n",
|
||||
RREG32(GRBM_STATUS2));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE0=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE0));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE1=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE1));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE2=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE2));
|
||||
dev_info(rdev->dev, " GRBM_STATUS_SE3=0x%08X\n",
|
||||
RREG32(GRBM_STATUS_SE3));
|
||||
dev_info(rdev->dev, " SRBM_STATUS=0x%08X\n",
|
||||
RREG32(SRBM_STATUS));
|
||||
dev_info(rdev->dev, " SRBM_STATUS2=0x%08X\n",
|
||||
RREG32(SRBM_STATUS2));
|
||||
evergreen_mc_resume(rdev, &save);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* cik_asic_reset - soft reset compute and gfx
|
||||
*
|
||||
* @rdev: radeon_device pointer
|
||||
*
|
||||
* Soft reset the CPC blocks (CIK).
|
||||
* XXX: make this more fine grained and only reset
|
||||
* what is necessary.
|
||||
* Returns 0 for success.
|
||||
*/
|
||||
int cik_asic_reset(struct radeon_device *rdev)
|
||||
{
|
||||
int r;
|
||||
|
||||
r = cik_compute_gpu_soft_reset(rdev);
|
||||
if (r)
|
||||
dev_info(rdev->dev, "Compute reset failed!\n");
|
||||
|
||||
return cik_gfx_gpu_soft_reset(rdev);
|
||||
}
|
||||
|
||||
/**
|
||||
* cik_sdma_is_lockup - Check if the DMA engine is locked up
|
||||
*
|
||||
|
|
@ -2938,13 +3031,15 @@ int cik_asic_reset(struct radeon_device *rdev)
|
|||
*/
|
||||
bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
|
||||
{
|
||||
u32 dma_status_reg;
|
||||
u32 reset_mask = cik_gpu_check_soft_reset(rdev);
|
||||
u32 mask;
|
||||
|
||||
if (ring->idx == R600_RING_TYPE_DMA_INDEX)
|
||||
dma_status_reg = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
|
||||
mask = RADEON_RESET_DMA;
|
||||
else
|
||||
dma_status_reg = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
|
||||
if (dma_status_reg & SDMA_IDLE) {
|
||||
mask = RADEON_RESET_DMA1;
|
||||
|
||||
if (!(reset_mask & mask)) {
|
||||
radeon_ring_lockup_update(ring);
|
||||
return false;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,7 +40,19 @@
|
|||
#define QUEUEID(x) ((x) << 8)
|
||||
|
||||
#define SRBM_STATUS2 0xE4C
|
||||
#define SDMA_BUSY (1 << 5)
|
||||
#define SDMA1_BUSY (1 << 6)
|
||||
#define SRBM_STATUS 0xE50
|
||||
#define UVD_RQ_PENDING (1 << 1)
|
||||
#define GRBM_RQ_PENDING (1 << 5)
|
||||
#define VMC_BUSY (1 << 8)
|
||||
#define MCB_BUSY (1 << 9)
|
||||
#define MCB_NON_DISPLAY_BUSY (1 << 10)
|
||||
#define MCC_BUSY (1 << 11)
|
||||
#define MCD_BUSY (1 << 12)
|
||||
#define SEM_BUSY (1 << 14)
|
||||
#define IH_BUSY (1 << 17)
|
||||
#define UVD_BUSY (1 << 19)
|
||||
|
||||
#define SRBM_SOFT_RESET 0xE60
|
||||
#define SOFT_RESET_BIF (1 << 1)
|
||||
|
|
|
|||
Loading…
Reference in New Issue