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clk: qoriq: add more PLL divider clocks support 

More PLL divider clocks are needed by clock consumer IP. So enlarge
the PLL divider array to accommodate more divider clocks.

Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
hifive-unleashed-5.2
Yuantian Tang 2019-04-22 17:15:09 +08:00 committed by Stephen Boyd
parent f34b2c26fc
commit cc61ab9ba2
1 changed files with 3 additions and 2 deletions
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5
drivers/clk/clk-qoriq.c
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@ -34,6 +34,7 @@
#define CGA_PLL4 4 /* only on clockgen-1.0, which lacks CGB */
#define CGB_PLL1 4
#define CGB_PLL2 5
#define MAX_PLL_DIV 16
struct clockgen_pll_div {
struct clk *clk;
@ -41,7 +42,7 @@ struct clockgen_pll_div {
};
struct clockgen_pll {
struct clockgen_pll_div div[8];
struct clockgen_pll_div div[MAX_PLL_DIV];
};
#define CLKSEL_VALID 1
@ -1128,7 +1129,7 @@ static void __init create_one_pll(struct clockgen *cg, int idx)
int ret;
/*
* For platform PLL, there are 8 divider clocks.
* For platform PLL, there are MAX_PLL_DIV divider clocks.
* For core PLL, there are 4 divider clocks at most.
*/
if (idx != PLATFORM_PLL && i >= 4)