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MIPS R2 instruction hazard handling. 

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Ralf Baechle 2005-07-12 18:35:38 +00:00
parent bbc7f22f6d
commit cc61c1fede
2 changed files with 17 additions and 0 deletions
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1
arch/mips/mm/c-r4k.c
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@ -529,6 +529,7 @@ static void r4k_flush_icache_range(unsigned long __user start,
args.end = end;
on_each_cpu(local_r4k_flush_icache_range, &args, 1, 1);
instruction_hazard();
}
/*

16
include/asm-mips/hazards.h
View File

@ -228,6 +228,22 @@ __asm__(
#endif
#if defined(CONFIG_CPU_MIPS32_R2) || defined (CONFIG_CPU_MIPS64_R2)
#define instruction_hazard() \
do { \
__label__ __next; \
__asm__ __volatile__( \
" jr.hb %0 \n" \
: \
: "r" (&&__next)); \
__next: \
; \
} while (0)
#else
#define instruction_hazard() do { } while (0)
#endif
#endif /* __ASSEMBLY__ */
#endif /* _ASM_HAZARDS_H */