Merge branch 'fsl_ucc_hdlc-enhancements'
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
commit
cc76169c93
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@ -293,9 +293,7 @@
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compatible = "fsl,ucc-hdlc";
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rx-clock-name = "clk9";
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tx-clock-name = "clk9";
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fsl,tx-timeslot-mask = <0xfffffffe>;
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fsl,rx-timeslot-mask = <0xfffffffe>;
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fsl,siram-entry-id = <0>;
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fsl,hdlc-bus;
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};
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};
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};
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@ -36,7 +36,6 @@
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#define DRV_NAME "ucc_hdlc"
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#define TDM_PPPOHT_SLIC_MAXIN
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#define BROKEN_FRAME_INFO
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static struct ucc_tdm_info utdm_primary_info = {
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.uf_info = {
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@ -99,6 +98,13 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
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uf_info->tsa = 1;
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uf_info->ctsp = 1;
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}
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/* This sets HPM register in CMXUCR register which configures a
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* open drain connected HDLC bus
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*/
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if (priv->hdlc_bus)
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uf_info->brkpt_support = 1;
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uf_info->uccm_mask = ((UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_RXF |
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UCC_HDLC_UCCE_TXB) << 16);
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@ -114,6 +120,9 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
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/* Loopback mode */
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if (priv->loopback) {
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dev_info(priv->dev, "Loopback Mode\n");
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/* use the same clock when work in loopback */
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qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
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gumr = ioread32be(&priv->uf_regs->gumr);
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gumr |= (UCC_FAST_GUMR_LOOPBACK | UCC_FAST_GUMR_CDS |
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UCC_FAST_GUMR_TCI);
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@ -133,11 +142,33 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
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/* Set UPSMR normal mode (need fixed)*/
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iowrite32be(0, &priv->uf_regs->upsmr);
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/* hdlc_bus mode */
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if (priv->hdlc_bus) {
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u32 upsmr;
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dev_info(priv->dev, "HDLC bus Mode\n");
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upsmr = ioread32be(&priv->uf_regs->upsmr);
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/* bus mode and retransmit enable, with collision window
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* set to 8 bytes
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*/
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upsmr |= UCC_HDLC_UPSMR_RTE | UCC_HDLC_UPSMR_BUS |
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UCC_HDLC_UPSMR_CW8;
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iowrite32be(upsmr, &priv->uf_regs->upsmr);
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/* explicitly disable CDS & CTSP */
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gumr = ioread32be(&priv->uf_regs->gumr);
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gumr &= ~(UCC_FAST_GUMR_CDS | UCC_FAST_GUMR_CTSP);
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/* set automatic sync to explicitly ignore CD signal */
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gumr |= UCC_FAST_GUMR_SYNL_AUTO;
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iowrite32be(gumr, &priv->uf_regs->gumr);
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}
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priv->rx_ring_size = RX_BD_RING_LEN;
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priv->tx_ring_size = TX_BD_RING_LEN;
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/* Alloc Rx BD */
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priv->rx_bd_base = dma_alloc_coherent(priv->dev,
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RX_BD_RING_LEN * sizeof(struct qe_bd *),
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RX_BD_RING_LEN * sizeof(struct qe_bd),
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&priv->dma_rx_bd, GFP_KERNEL);
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if (!priv->rx_bd_base) {
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@ -148,7 +179,7 @@ static int uhdlc_init(struct ucc_hdlc_private *priv)
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/* Alloc Tx BD */
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priv->tx_bd_base = dma_alloc_coherent(priv->dev,
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TX_BD_RING_LEN * sizeof(struct qe_bd *),
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TX_BD_RING_LEN * sizeof(struct qe_bd),
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&priv->dma_tx_bd, GFP_KERNEL);
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if (!priv->tx_bd_base) {
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@ -295,11 +326,11 @@ free_ucc_pram:
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qe_muram_free(priv->ucc_pram_offset);
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free_tx_bd:
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dma_free_coherent(priv->dev,
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TX_BD_RING_LEN * sizeof(struct qe_bd *),
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TX_BD_RING_LEN * sizeof(struct qe_bd),
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priv->tx_bd_base, priv->dma_tx_bd);
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free_rx_bd:
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dma_free_coherent(priv->dev,
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RX_BD_RING_LEN * sizeof(struct qe_bd *),
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RX_BD_RING_LEN * sizeof(struct qe_bd),
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priv->rx_bd_base, priv->dma_rx_bd);
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free_uccf:
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ucc_fast_free(priv->uccf);
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@ -314,8 +345,6 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
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struct qe_bd __iomem *bd;
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u16 bd_status;
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unsigned long flags;
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u8 *send_buf;
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int i;
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u16 *proto_head;
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switch (dev->type) {
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@ -352,16 +381,6 @@ static netdev_tx_t ucc_hdlc_tx(struct sk_buff *skb, struct net_device *dev)
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dev_kfree_skb(skb);
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return -ENOMEM;
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}
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pr_info("Tx data skb->len:%d ", skb->len);
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send_buf = (u8 *)skb->data;
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pr_info("\nTransmitted data:\n");
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for (i = 0; i < 16; i++) {
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if (i == skb->len)
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pr_info("++++");
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else
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pr_info("%02x\n", send_buf[i]);
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}
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spin_lock_irqsave(&priv->lock, flags);
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/* Start from the next BD that should be filled */
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@ -423,7 +442,6 @@ static int hdlc_tx_done(struct ucc_hdlc_private *priv)
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skb = priv->tx_skbuff[priv->skb_dirtytx];
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if (!skb)
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break;
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pr_info("TxBD: %x\n", bd_status);
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dev->stats.tx_packets++;
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memset(priv->tx_buffer +
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(be32_to_cpu(bd->buf) - priv->dma_tx_addr),
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@ -454,14 +472,12 @@ static int hdlc_tx_done(struct ucc_hdlc_private *priv)
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static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
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{
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struct net_device *dev = priv->ndev;
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struct sk_buff *skb;
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struct sk_buff *skb = NULL;
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hdlc_device *hdlc = dev_to_hdlc(dev);
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struct qe_bd *bd;
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u16 bd_status;
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u16 length, howmany = 0;
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u8 *bdbuffer;
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int i;
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static int entry;
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bd = priv->currx_bd;
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bd_status = ioread16be(&bd->status);
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@ -471,9 +487,6 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
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if (bd_status & R_OV_S)
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dev->stats.rx_over_errors++;
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if (bd_status & R_CR_S) {
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#ifdef BROKEN_FRAME_INFO
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pr_info("Broken Frame with RxBD: %x\n", bd_status);
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#endif
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dev->stats.rx_crc_errors++;
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dev->stats.rx_dropped++;
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goto recycle;
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@ -482,17 +495,6 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
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(priv->currx_bdnum * MAX_RX_BUF_LENGTH);
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length = ioread16be(&bd->length);
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pr_info("Received data length:%d", length);
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pr_info("while entry times:%d", entry++);
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pr_info("\nReceived data:\n");
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for (i = 0; (i < 16); i++) {
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if (i == length)
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pr_info("++++");
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else
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pr_info("%02x\n", bdbuffer[i]);
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}
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switch (dev->type) {
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case ARPHRD_RAWHDLC:
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bdbuffer += HDLC_HEAD_LEN;
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@ -531,7 +533,6 @@ static int hdlc_rx_done(struct ucc_hdlc_private *priv, int rx_work_limit)
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howmany++;
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if (hdlc->proto)
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skb->protocol = hdlc_type_trans(skb, dev);
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pr_info("skb->protocol:%x\n", skb->protocol);
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netif_receive_skb(skb);
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recycle:
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@ -566,7 +567,7 @@ static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
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/* Tx event processing */
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spin_lock(&priv->lock);
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hdlc_tx_done(priv);
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hdlc_tx_done(priv);
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spin_unlock(&priv->lock);
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howmany = 0;
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@ -597,7 +598,6 @@ static irqreturn_t ucc_hdlc_irq_handler(int irq, void *dev_id)
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uccm = ioread32be(uccf->p_uccm);
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ucce &= uccm;
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iowrite32be(ucce, uccf->p_ucce);
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pr_info("irq ucce:%x\n", ucce);
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if (!ucce)
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return IRQ_NONE;
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@ -688,7 +688,7 @@ static void uhdlc_memclean(struct ucc_hdlc_private *priv)
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if (priv->rx_bd_base) {
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dma_free_coherent(priv->dev,
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RX_BD_RING_LEN * sizeof(struct qe_bd *),
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RX_BD_RING_LEN * sizeof(struct qe_bd),
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priv->rx_bd_base, priv->dma_rx_bd);
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priv->rx_bd_base = NULL;
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@ -697,7 +697,7 @@ static void uhdlc_memclean(struct ucc_hdlc_private *priv)
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if (priv->tx_bd_base) {
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dma_free_coherent(priv->dev,
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TX_BD_RING_LEN * sizeof(struct qe_bd *),
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TX_BD_RING_LEN * sizeof(struct qe_bd),
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priv->tx_bd_base, priv->dma_tx_bd);
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priv->tx_bd_base = NULL;
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@ -855,7 +855,6 @@ static int uhdlc_suspend(struct device *dev)
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/* save power */
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ucc_fast_disable(priv->uccf, COMM_DIR_RX | COMM_DIR_TX);
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dev_dbg(dev, "ucc hdlc suspend\n");
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return 0;
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}
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@ -1001,7 +1000,7 @@ static int ucc_hdlc_probe(struct platform_device *pdev)
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struct device_node *np = pdev->dev.of_node;
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struct ucc_hdlc_private *uhdlc_priv = NULL;
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struct ucc_tdm_info *ut_info;
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struct ucc_tdm *utdm;
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struct ucc_tdm *utdm = NULL;
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struct resource res;
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struct net_device *dev;
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hdlc_device *hdlc;
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@ -1054,10 +1053,6 @@ static int ucc_hdlc_probe(struct platform_device *pdev)
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return -EINVAL;
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}
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/* use the same clock when work in loopback */
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if (ut_info->uf_info.rx_clock == ut_info->uf_info.tx_clock)
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qe_setbrg(ut_info->uf_info.rx_clock, 20000000, 1);
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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return -EINVAL;
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@ -1080,6 +1075,9 @@ static int ucc_hdlc_probe(struct platform_device *pdev)
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if (of_get_property(np, "fsl,ucc-internal-loopback", NULL))
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uhdlc_priv->loopback = 1;
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if (of_get_property(np, "fsl,hdlc-bus", NULL))
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uhdlc_priv->hdlc_bus = 1;
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if (uhdlc_priv->tsa == 1) {
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utdm = kzalloc(sizeof(*utdm), GFP_KERNEL);
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if (!utdm) {
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@ -78,6 +78,7 @@ struct ucc_hdlc_private {
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u16 tsa;
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bool hdlc_busy;
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bool loopback;
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bool hdlc_bus;
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u8 *tx_buffer;
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u8 *rx_buffer;
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@ -668,6 +668,10 @@ struct ucc_slow_pram {
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#define UCC_FAST_GUMR_CTSS 0x00800000
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#define UCC_FAST_GUMR_TXSY 0x00020000
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#define UCC_FAST_GUMR_RSYN 0x00010000
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#define UCC_FAST_GUMR_SYNL_MASK 0x0000C000
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#define UCC_FAST_GUMR_SYNL_16 0x0000C000
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#define UCC_FAST_GUMR_SYNL_8 0x00008000
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#define UCC_FAST_GUMR_SYNL_AUTO 0x00004000
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#define UCC_FAST_GUMR_RTSM 0x00002000
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#define UCC_FAST_GUMR_REVD 0x00000400
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#define UCC_FAST_GUMR_ENR 0x00000020
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@ -785,6 +789,11 @@ struct ucc_slow_pram {
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#define UCC_GETH_UPSMR_SMM 0x00000080
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#define UCC_GETH_UPSMR_SGMM 0x00000020
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/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
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#define UCC_HDLC_UPSMR_RTE 0x02000000
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#define UCC_HDLC_UPSMR_BUS 0x00200000
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#define UCC_HDLC_UPSMR_CW8 0x00007000
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/* UCC Transmit On Demand Register (UTODR) */
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#define UCC_SLOW_TOD 0x8000
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#define UCC_FAST_TOD 0x8000
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